ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 7

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

DIGITAL TIMING SPECIFICATIONS
V
All specifications T
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT
PIPELINE DELAY
1
2
3
4
5
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: C[9:0], Y[9:0], and S[9:0].
Video control: P_HSYNC , P_VSYNC , P_BLANK , S_HSYNC , and S_VSYNC .
Guaranteed by characterization.
Guaranteed by design.
DD
Data Setup Time, t
Data Hold Time, t
Control Setup Time, t
Control Hold Time, t
Digital Output Access Time, t
Digital Output Hold Time, t
SD
ED
HD
= 1.71 V to 1.89 V. PV
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
Component Outputs (1×)
Component Outputs (8×)
Component Outputs (1×)
Component Outputs (4×)
1
1
1
5
MIN
12
11
4
4
12
to T
11
4
4
DD
MAX
14
= 1.71 V to 1.89 V. V
4
(−40°C to +85°C), unless otherwise noted.
13
4
2, 3
AA
Conditions
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
ED oversampling disabled
ED oversampling enabled
HD oversampling disabled
HD oversampling enabled
= 2.6 V to 3.465 V. V
Rev. 0 | Page 7 of 88
1
DD_IO
= 2.97 V to 3.63 V.
Min
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
4.0
3.5
ADV7340/ADV7341
Typ
68
67
78
84
41
46
40
44
Max
12
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles