ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 16

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

ADV7340/ADV7341
P_HSYNC
P_BLANK
Y OUTPUT
P_VSYNC
Y9 TO Y2/
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Y9 TO Y0
*SELECTED BY SUBADDRESS 0x01, BIT 7.
S_HSYNC
Y9 TO Y0*
S_VSYNC
S9 TO S0/
Figure 17. HD-DDR, 8-/10-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
a
Figure 18. SD Input Timing Diagram (Timing Mode 1)
c
Rev. 0 | Page 16 of 88
b
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
Cb
Cb0
Y
Y0
Cr
Cr0
Y
Y1