ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 65

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power sensitive applications, the ADV7340/ADV7341
support an Analog Devices, Inc. proprietary low power mode of
operation on DAC 1, DAC 2, and DAC 3. To utilize this low
power mode, these DACs must be operating in full-drive mode
(R
low drive mode (R
can be independently enabled or disabled on DAC 1, DAC 2, and
DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is
disabled by default on each DAC.
In low power mode, DAC current consumption is content
dependent. On a typical video stream, it can be reduced by as
much as 40%. For applications requiring the highest possible video
performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10
The ADV7340/ADV7341 include an Analog Devices, Inc.
proprietary cable detection feature.
The cable detection feature is available on DAC 1 and DAC 2,
while operating in full-drive mode (R
assuming a connected cable). The feature is not available in low
drive mode (R
monitored, the DAC must be powered up in Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored, that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored, that is, the luma or green output is
monitored.
Once per frame, the ADV7340/ADV7341 monitor DAC 1
and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,
respectively. If a cable is detected on one of the DACs, the
relevant bit is set to 0. If not, the bit is set to 1.
DAC AUTO POWER-DOWN
Subaddress 0x10, Bit 4
For power sensitive applications, a DAC auto power-down feature
can be enabled using Subaddress 0x10, Bit 4. This feature is only
available when the cable detection feature is enabled.
SET
= 510 Ω, R
SET
L
= 4.12 kΩ, R
= 37.5 Ω). Low power mode is not available in
SET
= 4.12 kΩ, R
L
= 300 Ω). For a DAC to be
L
= 300 Ω). Low power mode
SET1
= 510 Ω, R
L1
= 37.5 Ω,
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With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame. If they are unconnected,
some or all of the DACs automatically power down. Which
DAC or DACs are powered down depends on the selected
output configuration.
For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is
unconnected, all three DACs power down. DAC 2 is not
monitored for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable
is detected, the appropriate DAC or DACs remain powered up
for the duration of the frame. If no cable is detected, the
appropriate DAC or DACs power down until the next frame
when the process is repeated.
PIXEL AND CONTROL PORT READBACK
Subaddress 0x12 to Subaddress 0x16
The ADV7340/ADV7341 support the readback of most digital
inputs via the I
board-level connectivity testing with upstream devices.
The pixel port (S[9:0], Y[9:0], and C[9:0]), the control port
( S_HSYNC , S_VSYNC , P_HSYNC , P_VSYNC and P_BLANK ),
and the SFL/MISO pin are available for readback via the MPU
port. The readback registers are located at Subaddress 0x12 to
Subaddress 0x16.
When using this feature, a clock signal should be applied to
the CLKIN_A pin in order to register the levels applied to the
input pins.
RESET MECHANISM
Subaddress 0x17, Bit 1
The ADV7340/ADV7341 have a software reset accessible via
the I
a 1 to Subaddress 0x17, Bit 1. This resets all registers to their
default values. This bit is self-clearing, that is, after a 1 has been
written to the bit, the bit automatically returns to 0.
When operating in SPI mode, a software reset does not cause
the device to revert to I
ADV7340/ADV7341 need to be powered down.
The ADV7340/ADV7341 include a power-on reset (POR)
circuit to ensure correct operation after power-up.
2
C/SPI MPU port. A software reset is activated by writing
2
C/SPI MPU port. This feature is useful for
2
C mode. For this to occur, the
ADV7340/ADV7341