ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 80

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

ADV7340/ADV7341
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7340/ADV7341 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition
of the field input indicates a new frame, that is, vertical retrace. The ADV7340/ADV7341 automatically blank all normally blank lines as
per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the S_VSYNC and S_VSYNC pins,
respectively.
HSYNC
HSYNC
FIELD
FIELD
HSYNC
HSYNC
FIELD
FIELD
260
522
HSYNC
VSYNC
DISPLAY
PIXEL
DATA
622
309
DISPLAY
DISPLAY
DISPLAY
523
261
623
310
524
262
624
311
EVEN FIELD
EVEN FIELD
263
525
Figure 110. SD Timing Mode 2 Odd-to-Even Field Transition (Master/Slave)
625
312
264
ODD FIELD
1
ODD FIELD
ODD FIELD
EVEN FIELD
265
313
2
1
EVEN FIELD
266
3
NTSC = 122 × CLOCK/2
314
PAL = 132 × CLOCK/2
2
Figure 111. SD Timing Mode 3, NTSC
Figure 112. SD Timing Mode 3, PAL
ODD FIELD
267
4
315
3
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268
5
VERTICAL BLANK
VERTICAL BLANK
316
4
VERTICAL BLANK
VERTICAL BLANK
269
6
NTSC = 858 × CLOCK/2
PAL = 864 × CLOCK/2
317
5
270
7
Cb
318
271
6
8
Y
272
319
7
Cr
9
273
10
320
Y
274
11
Cb
21
334
22
283
20
DISPLAY
335
23
284
21
DISPLAY
DISPLAY
336
285
DISPLAY
22