ADV7340EBZ AD [Analog Devices], ADV7340EBZ Datasheet - Page 27

• Manufacturer Part Number: ADV7340EBZ
• Manufacturer: AD [Analog Devices]

Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read sequences.
SPI OPERATION
The ADV7340/ADV7341 support a 4-wire serial (SPI-
compatible) bus connecting multiple peripherals. Two inputs,
master out slave in (MOSI) and serial clock (SCLK), and one
output, master in slave out (MISO), carry information between
a master SPI peripheral on the bus and the ADV7340/ADV7341.
Each slave device on the bus has a slave select pin that is
connected to the master SPI peripheral by a unique slave select
line. As such, slave device addressing is not required.
To invoke SPI operation, a master SPI peripheral (for example,
a microprocessor) should issue three low pulses on the ADV7340/
ADV7341 ALSB/ SPI_SS pin. When the encoder detects the
third rising edge on the ALSB/ SPI_SS pin, it automatically
switches to SPI communication mode. The ADV7340/ADV7341
remain in SPI communication mode until a reset or power-
down occurs.
To control the ADV7340/ADV7341, use the following protocol
for both read and write transactions. First, the master initiates a
data transfer by driving and holding the ADV7340/ADV7341
ALSB/ SPI_SS pin low. On the first SCLK rising edge after
ALSB/ SPI_SS has been driven low, the write command, defined
as 0xD4, is written to the ADV7340/ADV7341 over the MOSI
line. The second byte written to the MOSI line is interpreted as
the starting subaddress. Data on the MOSI line is written MSB
first and clocked on the rising edge of SCLK.
SEQUENCE
SEQUENCE
WRITE
READ
S SLAVE ADDR
S
S = START BIT
P = STOP BIT
SLAVE ADDR
SDA
SCL
LSB = 0
A(S)
A(S)
START ADDR R/W ACK SUBADDRESS ACK
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S
SUBADDR
SUBADDR
1–7
8
Figure 50. I
A(S)
A(S) S SLAVE ADDR
9
Figure 49. I
Rev. 0 | Page 27 of 88
2
DATA
1–7
C Read and Write Sequence
2
C Data Transfer
8
LSB = 1
A(S)
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
9
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. The user can also
access any unique subaddress register on a one-by-one basis.
In a write data transfer, 8-bit data bytes are written to the
ADV7340/ADV7341, MSB first, on the MOSI line immediately
after the starting subaddress. The data bytes are clocked into
the ADV7340/ADV7341 on the rising edge of SCLK. When all
data bytes have been written, the master completes the transfer
by driving and holding the ADV7340/ADV7341 ALSB/ SPI_SS
pin high.
In a read data transfer, after the subaddress has been clocked
in on the MOSI line, the ALSB/ SPI_SS pin is driven and held
high for at least one clock cycle. Then, the ALSB/ SPI_SS pin is
driven and held low again. On the first SCLK rising edge after
ALSB/ SPI_SS has been driven low, the read command, defined
as 0xD5, is written, MSB first, to the ADV7340/ADV7341 over
the MOSI line. Subsequently, 8-bit data bytes are read from the
ADV7340/ADV7341, MSB first, on the MISO line. The data
bytes are clocked out of the ADV7340/ADV7341 on the falling
edge of SCLK. When all data bytes have been read, the master
completes the transfer by driving and holding the ADV7340/
ADV7341 ALSB/ SPI_SS pin high.
A(S)
DATA
1–7
DATA
8
ACK
DATA
9
A(M)
STOP
P
A(S) P
DATA
ADV7340/ADV7341
A(M) P