ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet
ATAM510X-ILQY
Related parts for ATAM510X-ILQY
ATAM510X-ILQY Summary of contents
Page 1
Features • Programmable System Clock with Prescaler and Five Different Clock Sources – 8-MHz Crystal Oscillator (System Clock) – 32-kHz Crystal Oscillator – RC-oscillator Fully Integrated – RC-oscillator with External Resistor Adjustment – External Clock Input • Wide ...
Page 2
Figure 0-1. Block Diagram TE Test bit 4-bit CPU core I/O 4 Port 0 Port 1 Port 5 ATAM510 2 SCLIN OSCIN OSCOUT AV DD System Real time clock clock Sleep ROM RAM Watch- 256 x 4 ...
Page 3
Pin Configuration Figure 1-1. Pinning SSO44 Table 1-1. Pin Description Pin Symbol Function 1 VSS Circuit ground 2 BP53 I/O line of high current Port 5 – bit wise configurable 3 BP52 I/O line of high current Port 5 ...
Page 4
Table 1-1. Pin Description Pin Symbol Function 20 BP12 I/O line of Port 1 – automatic nibble wise configurable 21 BP11 I/O line of Port 1 – automatic nibble wise configurable 22 BP10 I/O line of Port 1 – automatic ...
Page 5
MARC4 Architecture 2.1 General Description The functionality, programming and pinning of the ATAM510 is compatible with the ATAR510 mask programmable microcontroller from Atmel. All on-chip modules are addressed and con- trolled with exactly the same programming code, so that ...
Page 6
Components of MARC4 Core The core contains ROM, RAM, ALU, a program counter, RAM address registers, an instruction decoder and an interrupt controller. The following sections describe each functional block in more detail. 2.2.1 EEPROM The program memory (EEPROM) ...
Page 7
Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arith- metic, I/O and memory reference operations take their operands from, and return their results to the expression stack. The MARC4 performs the ...
Page 8
RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. 2.3.3 Expression Stack Pointer (SP) The stack pointer ...
Page 9
Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, ...
Page 10
Interrupt Structure The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources software interrupt from the CPU itself. Each interrupt level has a hard-wired priority ...
Page 11
Figure 2-6. Interrupt Handling INT3 4 3 INT3 active Main / Autosleep Table 2-1. Interrupt Priority Table Interrupt Priority INT0 Lowest INT1 | INT2 | INT3 | INT4 | INT5 | INT6 INT7 Highest ...
Page 12
Table 2-2. Hardware Interrupts Possible Interrupt Priorities Interrupt Source 0 1 NRST external Watchdog Port A coded reset Port A monitor * Port B monitor * Port 60 external * Port 61 external * Interval timer INTA * Interval timer ...
Page 13
Hardware Reset The master reset forces the CPU into a well-defined condition unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power ...
Page 14
Table 2-3. NO_RST RST2 RST3 RST4 RST5 RST6 RST7 Note: 2.6.4 Watchdog Reset The watchdog’s function can be enabled via a mask option and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the counter must ...
Page 15
Clock Generation 2.7.1 Clock Module The clock module generates two clocks. The system clock (SYSCL) supplies the CPU and the peripherals while the lower frequency periphery sub-clock (SUBCL) supplies only the peripher- als. The modes for clock sources are ...
Page 16
Figure 2-9. Clock Module Ext. clock SCLIN ExIn RC-oscillator2 OSCIN R Trim 4-MHz oscillator Oscin Oscout 32-kHz oscillator Oscin OSCOUT Oscout Table 2-4. Mode 2.7.2 Oscillator Circuits and External Clock Input Stage 2.7.2.1 RC-oscillator 1 Fully ...
Page 17
Figure 2-10. RC-oscillator 1 2.7.2.2 External Input Clock The SCLIN pin can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. The maximum system clock frequency f the ...
Page 18
Figure 2-13. System Clock Oscillator 2.7.2.5 32-kHz Oscillator Some applications require accurate long-term time keeping without putting excessive demands on the CPU or alternatively low resolution computing power. In this case, the on-chip ultra low power 32-kHz crystal oscillator can ...
Page 19
Clock Management Register (CM) The clock management register controls the system clock divider chain, as well as the peripheral clock in power-down modes. CM NSTOP CCS CSS1 (1:0) Table 2-5. 2.7.4 System Configuration Register (SC) SC: write Table 2-6. ...
Page 20
OS1, OS0 Table 2-7. CCS Note: 2.7.5 Power-down Modes The ATAM510 incorporates several modes which enable the power consumption to be tailored to a minimum without sacrificing computational power. When the controller exits the lowest ...
Page 21
Clock Monitor Mode Figure 2-15. Clock Monitoring NRST TE BP11 BP10 For trimming purposes, the ATAM510 can be put into a clock monitor mode. By forcing the test input (TE) high, the SYSCL clock will appear on BP11 (Port ...
Page 22
Figure 3-1. Example of I/O Addressing Module ASW (Address Pointer) Auxiliary Switch Module Primary Reg Example of qFORTH Program 1 Code ATAM510 22 Module M1 ...
Page 23
Table 3-1. Peripheral Addresses Port Address Name 0 P0DAT 1 P1DAT 2 PAIPR Auxiliary PAICR 3 CWD PBIBR Auxiliary PBICR 4 P4DAT Auxiliary P4DDR 5 P5DAT Auxiliary P5DDR 6 P6DAT Auxiliary P6CR 7 P7DAT Auxiliary P7DDR 8 ASW 9 TCM ...
Page 24
Bi-directional Ports Table 3-2. Overview of Port Features Port Address 0 Number of bits 4 Bit wise programmable no direction Output drivers mask (2) no (1) configurable Dynamic pull-up/-down typ. 500k (3) (Ohm) Static pull-up/-down typ. none (4) (Ohm) ...
Page 25
Port Data Register (PxDAT) PxDAT Bit 3 = MSB, Bit 0 = LSB Port address 3.2.2 Port Data Direction Register (PxDDR) PxDDR Table 3-3. Code ...
Page 26
Figure 3-2. 3.2.4 Bi-directional Port 5, Port 7 and Port C All bi-directional ports except Port 0 and Port 1, include a bit wise programmable Data Direction Register (PxDDR) which allows the individual programming of each port bit as input ...
Page 27
Bi-directional Port A and Port B with Port Monitor Function Figure 3-4. Port Monitor Module of Port A and Port B Connected to Ports A and PxICR BPx3 BPx2 BPx1 BPx0 In addition ...
Page 28
Table 3-4. Code 3.2.5.2 ...
Page 29
Bi-directional Port 6 Figure 3-5. This 2-bit bi-directional port can be used as a bit wise programmable I/O. The data is LSB aligned so that the two MSB's will not appear on the port pins when written. The port ...
Page 30
Port 6 Data Register (P6DAT) P6DAT The unused bits 2 and 3 are 0, if read. 3.2.6.2 Port 6 Control Register (P6CR) P6CR P6xIM2, P6xIM1 - Port 6x interrupt mode/direction code P6xPR2, P6xPR1 - BP6x interrupt priority code Table ...
Page 31
Figure 3-6. 3.2.7 Bi-directional Port 4 The bi-directional Port 4 is both a bit wise configurable I/O port and provides the external pins for both the Timer 0 and the internal buzzer generator I/O port, it performs in ...
Page 32
TIM1 - Dedicated Timer 1 I/O Pin Figure 3-8. TIM1 is a dedicated bi-directional I/O stage for signal communication to and from Timer 1 in the timer/counter module (see from the CPU. Direction control is performed from the timer/counter ...
Page 33
Figure 3-9. 3.3.1 Interval Timer Registers The Interval Timer Frequency Select Register (ITFSR) is I/O mapped to the primary address register of the prescaler/interval timer address ('F'hex) and the Interval Timer Interrupt Priority Register (ITIPR) to the corresponding auxiliary register. ...
Page 34
Table 3-7. Code ...
Page 35
The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2-FS0). This allows independent programming of interval times for INTA and INTB. 3.4 Watchdog Timer Figure 3-10. Watchdog Timer The watchdog ...
Page 36
Each timer represents a single maskable interrupt source (T0INT and T1INT), the priority of which can be configured under program control. A Timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). The associated status ...
Page 37
General Timer/Counter Control Registers With the exception of the Timer 0 Interrupt Status Register (T0SR), all the timer/counter regis- ters are indirectly addressed using extended addressing as described in the section “Addressing Peripherals”. An overview of all register and ...
Page 38
Timer/Counter Interrupt Priority Register (TCIP) The Timer/Counter Interrupt Priority register (TCIP) is used to configure Timer 0 and Timer 1 interrupt priority levels. TCIP T0IP2, T0IP1 - Timer 0 Interrupt Priority code T1IP2, T1IP1 - Timer 1 Interrupt Priority ...
Page 39
Table 3-11. Code ...
Page 40
Timer/Counter Mode Register (TCMO) TCMO T0NINV TC8 T1STP T0STP Table 3-12. Code ...
Page 41
In 16-bit mode, Timer 0 and Timer 1 are cascaded thus forming a 16-bit counter (see 13) whereby, irrespective of the state of Timer 0 interrupt mask bit (T0IM), the Timer 1 counts both Timer 0 overflow and compares interrupt ...
Page 42
Table 3-13. Timer 0 Mode Register (T0MO) Code 3210 Function Reserved Reserved Modulated melody mode Melody mode Counter-auto reload (50% ...
Page 43
Table 3-14. The interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding interrupt is triggered. Therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. To see ...
Page 44
Timer 0 Compare Register (T0CP) - Byte Write T0CP T0CP3 ... T0CP0 - Timer 0 Compare Register Data (low nibble) - first write cycle T0CP7 ... T0CP4 - Timer 0 Compare Register Data (high nibble) - second write cycle ...
Page 45
Figure 3-14. Timer 0 Free Running Counter Mode Timer State Overflow Interrupt strobe T0OUT1 (BP41) 50% duty cycle Timer Clock Timer resets on overflow 3.5.3.7 Timer 0 Counter Reload Modes (Strobe and 50% Duty Cycle the free running ...
Page 46
Melody Mode (with/without Modulation) The non-modulated melody mode is identical to the auto-reload counter (50% duty cycle) mode. The melody tone frequency appearing on BP41 and/or BP40 is determined in exactly the same way as the value written into ...
Page 47
Timer 0 Pulse Width Modulation Mode A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark space ratio often used as a simple method for D/A conversion, where the high period is ...
Page 48
Figure 3-19. An Example 4-bit PWM/PDM Comparison PWM = 0.25 PWM = 0.75 PDM = 0.25 PDM = 0.75 3.5.3.11 Period Measurement Modes (Rising and Falling Edge) During the period measurement mode, the counter counts the number of either internal ...
Page 49
Figure 3-21. Pulse Width Measurement "eom" Interrupt T0IN1 (BP41) 3.5.3.13 Phase Measurement Mode This mode allows the Timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the BP40 and BP41 pins (see ...
Page 50
Figure 3-23. Position Measurement Mode Typical sensor left movement Timer N N+1 T0IN0 (BP40) T0IN1 (BP41) 3.5.4 Timer 1 Modes ...
Page 51
Table 3-16. Code 3.5.4.2 ...
Page 52
Timer 1 Compare Register (T1CP) - Byte Write T1CP T1CP3 ... T1CP0 - Timer 1 Compare Register Data (low nibble) - first write cycle T1CP7 ... T1CP4 - Timer 1 Compare Register Data (high nibble) - second write cycle ...
Page 53
Timer 1 Counter Free Running (50% Duty Cycle) In the free running counter mode, the counter counts up with either an internal or external clock and cycles through all 256 timer states. On the clock following a match between ...
Page 54
Timer 1 Pulse Width Modulation The Timer 1 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see compare register value, then the TIM1 output is high. ...
Page 55
Buzzer Module The buzzer stage frequency divider which divides the SUBCL and depending on the state of the Buzzer Control Register (BZCR) can output one of four frequencies. An external piezo or buzzer can be driven ...
Page 56
Table 3-18. Code Figure ...
Page 57
To accommodate the application program and the associated hardware option configuration, the ATAM510 is equipped with 2 on-chip EEPROM memory blocks. These are written via a 6-signal Target Programmer Interface (TPI), comprising of 2 power lines (VDD and VSS), a ...
Page 58
Read Lock Protection The programmer software incorporates a so called “Read Lock” which can be set by the user. This is provided for customer security purposes and inhibits the reading of the customer's Appli- cation Program by unauthorized persons. ...
Page 59
Noise Considerations When designing the microcontroller based application, several factors should be taken into con- sideration to increase noise immunity and reduce electromagnetic emissions (EME). Many such potential problems can be avoided by careful layout of the printed circuit ...
Page 60
Absolute Maximum Ratings Voltages are given relative to V SS. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...
Page 61
DC Operating Characteristics (Continued) Supply voltage Typical values relate amb Parameters Input NRST with Pull-up Resistor Input LOW current Input TE ...
Page 62
AC Characteristics Supply voltage V = 2 Typical values relate amb Parameters Reset Timing Power-on reset delay NRST input LOW time Interrupt Request Input Timing Interrupt ...
Page 63
AC Characteristics (Continued) Supply voltage V = 2 Typical values relate amb Parameters External Clock Input at SCLIN, TIM1 and T0IN SCLIN input clock f = ...
Page 64
Figure 7-2. Figure 7-3. Figure 7-4. ATAM510 64 Worst Case Minimum/Maximum System Frequency (Using External RC or Crystal Oscillator) 100.000 10.000 f SYSCLmax 1.000 0.100 0.010 0.001 ...
Page 65
Figure 7-5. Figure 7-6. Figure 7-7. 4711B–4BMCU–01/ External RC SYSCL amb 2200 2150 2100 2050 DD 2000 1950 1900 -40 - (°C) amb ...
Page 66
Figure 7-8. Figure 7-9. Figure 7-10. f ATAM510 Internal RC SYSCL DD 7000 6000 5000 4000 3000 2000 1000 0 1.5 2.5 3 ...
Page 67
Figure 7-11. Typical High Output Driver, V Figure 7-12. Typical Low Output Driver, V Figure 7-13. Typical Low Output Driver, V 4711B–4BMCU–01/ -10 -12 0.0 0.5 1.0 1 ...
Page 68
Figure 7-14. Typical High Output Driver Pad Layout Emulation The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software ...
Page 69
... Ordering Information Extended Type Number ATAM510x-ILQY ATAM510x-ILSY Note Hardware revision Y = Lead-free 10. Package Information Package SSO44 Dimensions in mm 0.3 0 4711B–4BMCU–01/05 Program Memory Data-EEPROM 4 kB ROM ROM No 18.05 17.80 16 Package Delivery SSO44 Taped and reeled SSO44 Tubes 9.15 8.65 7.50 7.30 2.35 0.25 0.10 10.50 10.20 technical drawings according to DIN ...
Page 70
Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4711B-4BMCU-01/05 ATAM510 70 History Put datasheet in a new template Features on page ...
Page 71
Table of Contents Features ..................................................................................................... 1 Description ................................................................................................ 1 1 Pin Configuration ..................................................................................... 3 2 MARC4 Architecture ................................................................................ 5 3 Peripheral Modules ................................................................................ 21 4 Absolute Maximum Ratings .................................................................. Operating Characteristics ............................................................... Characteristics ...
Page 72
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...