ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 21
ATAM510X-ILQY
Manufacturer Part Number
ATAM510X-ILQY
Description
MARC4 4-bit MTP Universal Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM510X-ILQY.pdf
(72 pages)
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2.7.6
Figure 2-15. Clock Monitoring
3. Peripheral Modules
3.1
4711B–4BMCU–01/05
Addressing Peripherals
Clock Monitor Mode
NRST
BP11
TE
BP10
For trimming purposes, the ATAM510 can be put into a clock monitor mode. By forcing the test
input (TE) high, the SYSCL clock will appear on BP11 (Port 1, bit 1) and SUBCL clock on Port
BP10 (Port 1, bit 0). On releasing the TE pin, the BP10 and BP11 will resume their normal func-
tion (see
Accessing the peripheral modules takes place via the I/O bus (see
IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register address-
ing scheme has been adopted which addresses the “primary register” directly. To address the
“auxiliary register”, the access must be switched with an “auxiliary switching module”. Thus, a
single IN (or OUT) to the module address will read (or write) into the module primary register.
Accessing the auxiliary register is performed with the same instruction preceded by writing the
module address into the auxiliary switching module. Byte-wide registers are accessed by multi-
ple IN (or OUT) instructions. Extended addressing is used for more complex peripheral modules,
with a larger number of registers. In this case, a bank of up to 16 subport registers are indirectly
addressed with the subport address being initially written into the auxiliary register. Please refer
to the “HARDC510.SCR” hardware interface file as a programming guideline.
Figure
2-15).
Oscillator supervisory mode
SYSCL clocks
SUBCL clocks
Figure 3-1 on page
Normal operation
ATAM510
22). The
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