ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 54

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ATAM510X-ILQY

Manufacturer Part Number
ATAM510X-ILQY
Description
MARC4 4-bit MTP Universal Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
3.5.4.7
Figure 3-26. Timer 1 Pulse Width Modulation
54
Timer
State
Compare
Interrupt
T1OUT
(TIM1)
Timer
Clock
t_hi = (comparator value)
t_low = (256-comparator value)
ATAM510
Timer 1 Pulse Width Modulation
The Timer 1 generates the PWM signal by comparing the state of the free running up counter
with the contents of the compare register (see
compare register value, then the TIM1 output is high. If the result is greater than the compare
register value, then the TIM1 output is set low. Thus, the high phase of the PWM signal is
directly proportional to the compare register contents. A total of 256 possible discrete mark
space ratios can be generated ranging from a continuous low signal over a variable pulse width
signal. The PWM signal has a repetition period of 256 clock periods, an interrupt (if unmasked)
being generated on every compare event.
Care should be taken if SYSCL is used as the PWM clock source. The PWM output may stop if
the CPU goes into SLEEP mode depending on the programming of the NSTOP bit in the CM-
register. If using this mode of operation it is recommended to set the bit NSTOP =1.
clock period
255
clock period
0
1
t_hi
2
3
4
Timer = compare register (= 4)
t_low
255
0
1
2
Figure
3
4
3-26). If the result is less or equal to the
255
0
1
2
3
4
4711B–4BMCU–01/05

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