ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 19

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

2.7.3
2.7.4
4711B–4BMCU–01/05
Clock Management Register (CM)
System Configuration Register (SC)
The clock management register controls the system clock divider chain, as well as the peripheral
clock in power-down modes.
Table 2-5.
Table 2-6.
NSTOP
CCS
CSS1 (1:0)
CM
SC: write
RC1
0
0
1
1
CSS1
0
0
1
1
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external
Core Speed Select
These two bits control the system clock divider chain
Bit 3
NSTOP
Core Speed Select
Internal RC Oscillator 1 Frequency Selection (SYSCL
RC0
0
1
0
1
Bit 3
RC1
clock source or the RC-oscillator 2 (with the external resistor) will
generate SYSCL dependent on the setting of OS0 and OS1 in the
system configuration register
The 32-kHz crystal oscillator SUBCL clock cannot be stopped
Bit 2
CCS
SYSCL
7.0 MHz (f
3.0 MHz (f
2.0 MHz (f
0.8 MHz (f
Bit 2
RC0
max
CSS0
Bit 1
CSS1
iRC0
iRC1
iRC2
iRC3
0
1
0
1
at 25°C, V
)
)
)
)
Bit 1
OS1
Bit 0
CSS0
DD
= 5 V
Bit 0
OS0
Auxiliary register address:
Reset value: 1111b
Divider
16
Primary register address: ’E’hex
Reset value: 1111b
8
4
2
max
)
Reset value = SYSCL
Note
–
–
–
Reset value
ATAM510
’E’hex
SYSCL
SYSCL
SYSCL
Note
max
max
max
/8
/4
/2
max
19