ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 9

• Manufacturer Part Number: ATAM510X-ILQY
• Description: MARC4 4-bit MTP Universal Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

2.3.10
2.4
2.4.1
2.4.2
4711B–4BMCU–01/05
ALU
Interrupt Enable (I)
Instruction Set
I/O Bus
The interrupt enable flag globally enables or disables the triggering of all interrupt routines with
the exception of the non-maskable reset. After a reset or while executing the DI instruction, the
interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further
interrupt requests until the interrupt enable flag has been set again by either executing an EI or
SLEEP instruction.
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele-
ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU
operations affect the carry/borrow and branch flag in the condition code register (CCR).
Figure 2-5.
The MARC4 instruction set is optimized for the high level programming language qFORTH.
Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and
compact program code. The CPU has an instruction pipeline which allows the controller to
prefetch an instruction from EEPROM at the same time as the present instruction is being exe-
cuted. The MARC4 is a zero-address machine, the instructions contain only the operation to be
performed and no source or destination address fields. The operations are implicitly performed
on the data placed on the stack. There are one and two byte instructions which are executed
within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock
cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single
machine cycle.
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication
between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O
control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip periph-
erals is described in the section “Peripheral Modules”. The I/O bus is internal and is not
accessible by the customer on the final microcontroller device, but it is used as the interface for
the MARC4 emulation.
ALU Zero-address Operations
SP
RAM
TOS-1
TOS-2
TOS-3
TOS-4
CCR
ALU
TOS
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