PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 130

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
14.3.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
14.3.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
FIGURE 14-8: I
FIGURE 14-9: I
DS39026B-page 130
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
SDA
SSPIF
SCL
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S
S
RECEPTION
TRANSMISSION
A7 A6 A5 A4 A3 A2 A1
1
A7
2
1
Data in
sampled
Receiving Address
2
2
3
C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A6
2
4
A5
Receiving Address
3
5
A4
4
6
7
A3
5
R/W=0
8
A2
6
ACK
9
A1
7
D7
1
D6
R/W = 1
2
8
Cleared in software
SSPBUF register is read
Receiving Data
D5
Preliminary
3
9
ACK
responds to SSPIF
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
while CPU
SCL held low
D3
5
D2
6
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 14-9).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the mas-
ter-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for
another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR
register. Pin RC3/SCK/SCL should be enabled by
setting bit CKP.
D1
7
D7
1
SSPBUF is written in software
D0
8
ACK
D6
9
Cleared in software
2
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D7
1
D5
3
D6
2
D4
4
D5
Receiving Data
3
Transmitting Data
D3
D4
4
5
ACK is not sent.
D3
5
D2
7/99 Microchip Technology Inc.
6
D2
6
From SSP interrupt
service routine
D1
7
D1
7
D0
8
D0
8
R/W = 0
Not ACK
Not ACK
9
9
Bus Master
terminates
transfer
P
P