PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 138

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
14.3.7
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
module is in the idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (T
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is re-loaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high for one T
then followed by assertion of the SDA pin (SDA = 0) for
one T
bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin held low. As soon as a start condition is
detected on the SDA and SCL pins, the S bit (SSP-
STAT<3>) will be set. The SSPIF bit will not be set until
the baud rate generator has timed-out.
FIGURE 14-17: REPEAT START CONDITION WAVEFORM
DS39026B-page 138
Note 1: If RSEN is programmed while any other
Note 2: A bus collision during the Repeated Start
BRG,
I
CONDITION TIMING
2
C MASTER MODE REPEATED START
while SCL is high. Following this, the RSEN
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
BRG
Falling edge of ninth clock
). When the baud rate generator
SDA
SCL
End of Xmit
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
BRG
. This action is
2
C logic
Preliminary
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
14.3.7.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note:
Sr = Repeated Start
T
BRG
At completion of start bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
WCOL STATUS FLAG
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
and set SSPIF
Write to SSPBUF occurs here.
T
BRG
1st Bit
T
BRG
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