PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 223

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
7/99 Microchip Technology Inc.
After Interrupt
operation
Decode
No
PC
Q1
= TOS
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The
stack is popped and the top of the
stack (TOS) is loaded into the
program counter. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
1
2
RETURN
0000
No
No
Q2
[0,1]
WREG,
PC,
RETURN s
0000
BSR,
operation
Process
Data
STATUS,
No
Q3
0001
pop PC from
operation
stack
No
Q4
001s
Preliminary
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
C
REG
WREG
C
Q1
=
=
=
=
=
register ’f’
Rotate Left f through Carry
[ label ] RLCF
0
d
a
(f<n>)
(f<7>)
(C)
C,N,Z
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
f
PIC18CXX2
[0,1]
[0,1]
C
dest<0>
255
dest<n+1>,
C,
01da
Process
REG, 0, 0
Data
Q3
register f
DS39026B-page 223
f,d,a
ffff
destination
Write to
Q4
ffff