PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 144

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
14.3.12 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated start/stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 14-22).
FIGURE 14-22: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
DS39026B-page 144
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
SCL
SDA
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
BRG
Preliminary
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
14.3.13 SLEEP OPERATION
While in sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor from
sleep (if the MSSP interrupt is enabled).
14.3.14 EFFECT OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
T
SCL = 1 BRG starts counting
clock high interval.
BRG
7/99 Microchip Technology Inc.
2
C module can receive
OSC
² 4).