PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 188

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
18.3.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
• If the interrupt condition occurs during or after
FIGURE 18-3: WAKE-UP FROM SLEEP THROUGH INTERRUPT
DS39026B-page 188
Note 1: XT, HS or LP oscillator mode assumed.
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
the execution of a SLEEP instruction, the device
will immediately wake up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIEH bit
(INTCON<7>)
Instruction
fetched
CLKOUT
Instruction
executed
2: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0',
3: T
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
INT pin
OSC1
WAKE-UP USING INTERRUPTS
PC
(4)
execution will continue in-line.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
Q1 Q2 Q3 Q4
(drawing not to scale) This delay will not occur for RC and EC osc modes.
Inst(PC + 2)
SLEEP
PC+2
Q1
Processor in
SLEEP
PC+4
Preliminary
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 4)
Inst(PC + 2)
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
PC+4
Interrupt Latency
Dummy cycle
(1,2)
PC + 4
(3)
Q1 Q2 Q3 Q4
Inst(0008h)
Dummy cycle
7/99 Microchip Technology Inc.
0008h
Q1 Q2 Q3 Q4
Inst(000Ah)
Inst(0008h)
000Ah