PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 67

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

7.0.1
The INTCON Registers are readable and writable
registers, which contains various enable, priority and
flag bits.
Register 7-1:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
7/99 Microchip Technology Inc.
INTCON REGISTERS
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all un-masked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all interrupts
0 = Disables all interrupts
PEIE/GEIL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all priority peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
GIE/GIEH
Legend:
R = Readable bit
- n = Value at POR reset
Note:
R/W-0
INTCON Register
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
PEIE/GIEL
R/W-0
TMR0IE
R/W-0
W = Writable bit
’1’ = Bit is set
INT0IE
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
RBIE
TMR0IF
R/W-0
x = Bit is unknown
INT0IF
R/W-0
PIC18CXX2
bit 0
R/W-x
RBIF
DS39026B-page 67