PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 46

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
TABLE 4-2:
4.10
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
DS39026B-page 46
Filename
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
LATD
LATC
LATB
LATA
PORTE
PORTD
PORTC
PORTB
PORTA
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only and read ’0’ in all
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: Other (non-power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Access Bank
other oscillator modes.
Bit 7
PSPIP
PSPIF
PSPIE
IBF
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (Cont.’d)
Bit 6
ADIP
ADIF
ADIE
OBF
TRISA6
LATA6
RA6
—
—
—
—
(1)
(1)
(1)
Bit 5
RCIP
RCIF
RCIE
IBOV
Data Direction Control Register for PORTA
Read PORTA Data Latch, Write PORTA Data Latch
Read PORTA pins, Write PORTA Data Latch
—
—
—
—
Bit 4
TXIP
TXIF
TXIE
PSP-
MODE
—
—
—
—
Preliminary
Bit 3
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
—
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers so that these registers
can be accessed without any software overhead. This
is useful for testing status flags and modifying control
bits.
Bit 2
LVDIP
LVDIF
LVDIE
CCP1IP
CCP1IF
CCP1IE
Data Direction bits for PORTE
Read PORTE Data Latch, Write
PORTE Data Latch
(1)
(1)
Bit 1
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
Bit 0
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
7/99 Microchip Technology Inc.
Value on
POR,
BOR
---- 1111
---- 0000
---- 0000
1111 1111
0000 0000
0000 0000
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
---- -000
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000
Value on
all other
resets
(note 3)
---- 1111
---- 0000
---- 0000
1111 1111
0000 0000
0000 0000
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
---- -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000