PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 17

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PIC18C242

Manufacturer Part Number
PIC18C242
Description
High-Performance Microcontrollers with 10-Bit A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

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FIGURE 2-4:
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes Bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
FIGURE 2-5:
FIGURE 2-6:
7/99 Microchip Technology Inc.
Clock from
ext. system
Clock from
ext. system
(from configuration
bit register)
OSC2
OSC1
F
RA6
OSC
EXTERNAL CLOCK INPUT
OPERATION
(EC OSC CONFIGURATION)
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
PLL BLOCK DIAGRAM
/4
Crystal
PLL Enable
Osc
HS Osc
OSC1
OSC2
OSC1
I/O (OSC2)
F
PIC18CXXX
PIC18CXXX
IN
Comparator
F
OUT
Phase
Preliminary
Loop
Filter
2.5
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC<2:0> con-
figuration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T
Divide by 4
HS/PLL
VCO
PIC18CXX2
PLL
DS39026B-page 17
.
SYSCLK

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