AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 117

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Command Receiver
4109E–8051–06/03
User may abort command loading by setting and clearing the CTPTR bit in MMCON0
register which resets the write pointer to the transmit FIFO.
Figure 82. Command Transmission Flow
The end of the response reception is signalled to you by the EORI flag in MMINT regis-
ter. This flag may generate an MMC interrupt request as detailed in Section "Interrupt",
page 124. When this flag is set, 2 other flags in MMSTA register: RESPFS and CRC7S
give a status on the response received. RESPFS indicates if the response format is cor-
rect or not: the size is the one expected (48 bits or 136 bits) and a valid End bit has been
received, and CRC7S indicates if the CRC7 computation is correct or not. These Flags
are cleared when a command is sent to the card and updated when the response has
been received.
User may abort response reading by setting and clearing the CRPTR bit in MMCON0
register which resets the read pointer to the receive FIFO.
According to the MMC specification delay between a command and a response (for-
mally N
the MMC controller when card does not send its response (e.g. physically removed from
the bus), user must launch a time-out period to exit from such situation. In case of time-
out user may reset the command controller and its internal state machine by setting and
clearing the CCR bit in MMCON2 register.
This time-out may be disarmed when receiving the response.
CR
parameter) can not exceed 64 MMC clock periods. To avoid any locking of
Configure Response
Transmission
RESPEN = X
Command
CRCDIS = X
RFMT = X
Transmit Command
MMCMD = argument
Load Command in
MMCMD = index
CMDEN = 1
CMDEN = 0
Buffer
AT8xC51SND1C
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