AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 123

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 88. Data Block Reception Flows
Flow Control
4109E–8051–06/03
read 8 data from MMDAT
a. Polling mode
Start Transmission
F1EI or F2EI = 1?
FIFO Reading
No More Data
Data Block
To Receive?
Reception
DATEN = 1
DATEN = 0
FIFO Full?
To allow transfer at high speed without taking care of CPU oscillator frequency, the
FLOWC bit in MMCON2 allows control of the data flow in both transmission and
reception.
During transmission, setting the FLOWC bit has the following effects:
•
•
During reception, setting the FLOWC bit has the following effects:
•
•
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the
clock is restored by writing or reading data in MMDAT.
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
Unmask FIFOs Full
Start Transmission
Initialization
Data Block
DATEN = 1
DATEN = 0
F1FM = 0
F2FM = 0
b. Interrupt mode
read 8 data from MMDAT
F1EI or F2EI = 1?
Reception ISR
Mask FIFOs Full
AT8xC51SND1C
FIFO Reading
No More Data
Data Block
To Receive?
FIFO Full?
F1FM = 1
F2FM = 1
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