AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 15

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Registers
4109E–8051–06/03
Table 16. CKCON Register
CKCON (S:8Fh) – Clock Control Register
Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83C51SND1C)
Table 17. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
Reset Value = 0000 1000b
Number
Number
5 - 3
7 - 6
5 - 4
Bit
Bit
R1
7
7
-
7
6
2
1
0
3
2
1
0
Mnemonic Description
Mnemonic Description
PLLRES
PLOCK
WDX2
PLLEN
WDX2
T1X2
T0X2
R1:0
Bit
R0
Bit
X2
6
6
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
Reserved
The values read from these bits are indeterminate. Do not set these bits.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, F
F
Set to select 6 clock periods per machine cycle (X2 mode, F
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
Reserved
The values read from these bits are always 0. Do not set these bits.
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
Reserved
The value read from this bit is always 0. Do not set this bit.
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
OSC
/
5
5
2).
-
-
4
4
-
-
PLLRES
3
3
-
AT8xC51SND1C
T1X2
2
2
-
PLLEN
T0X2
1
CPU
1
= F
CPU
PER
= F
PLOCK
= F
X2
PER
0
0
OSC
=
15
).