AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 151

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AT83C51SND1C_03

Manufacturer Part Number
AT83C51SND1C_03
Description
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Interrupt
4109E–8051–06/03
The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault”
flags.
As shown in Figure 118, these flags are combined toghether to appear as a single inter-
rupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out
and is cleared by reading SPSTA and then reading from or writing to SPDAT.
The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and
then writing to SPCON.
The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter-
rupts are globally enabled by setting EA bit in IEN0 register.
Figure 118. SPI Interrupt System
SPSTA.7
SPSTA.4
MODF
SPIF
IEN1.2
ESPI
AT8xC51SND1C
SPI Controller
Interrupt Request
151

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