AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 97

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

USB Interrupt System
Interrupt System Priorities
USB Interrupt Control System
4109E–8051–06/03
D+
D-
Controller
USB
Figure 68. USB Interrupt Control System
Table 1. Priority Levels
As shown in Figure 69, many events can produce a USB interrupt:
•
•
•
•
•
•
•
•
TXCMPL: Transmitted In Data (Table 96 on page 103). This bit is set by hardware
when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (Table 96 on page 103). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 96 on
page 103). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
RXSETUP: Received Setup (Table 96 on page 103). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 96 on
page 103). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
SOFINT: Start of Frame Interrupt (Table 92 on page 100). This bit is set by hardware
when a USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (Table 92 on page 100). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (Table 92 on page 100). This bit is set by hardware when
a USB suspend is detected on the USB bus.
IPHUSB
0
0
1
1
EUSB
IE1.6
Interrupt Enable
IE0.7
EA
IPLUSB
0
1
0
1
Priority Enable
IPH/L
00
01
10
11
Lowest Priority Interrupts
AT8xC51SND1C
3..................Highest
USB Priority Level
0..................Lowest
1
2
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