AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 49

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 26. Power-down Exit Waveform Using INT1:0
Figure 27. Power-down Exit Waveform Using KIN3:0
Note:
4109E–8051–06/03
1. KIN3:0 can be high or low-level triggered.
KIN3:0
INT1:0
OSC
OSC
1
Active phase
Active phase
Note:
2. Generate a reset.
Notes:
–
resumes when the input is released (see Figure 26) while using KINx input,
execution resumes after counting 1024 clock ensuring the oscillator is
restarted properly (see Figure 27). This behavior is necessary for decoding
the key while it is still pressed. In both cases, execution resumes with the
interrupt service routine. Upon completion of the interrupt service routine,
program execution resumes with the instruction immediately following the
instruction that activated Power-down mode.
1. The external interrupt used to exit Power-down mode must be configured as level
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the AT8xC51SND1C and
vectors the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
Power-down Phase
Power-down Phase
sensitive (
duration of the interrupt must be long enough to allow the oscillator to stabilize. The
execution will only resume when the interrupt is deasserted.
RAM content.
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
RAM content.
INT0
and
INT1
1024 clock count
Oscillator Restart Phase
) and must be assigned the highest priority. In addition, the
AT8xC51SND1C
Active phase
Active Phase
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