AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 95

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Suspend/Resume Management
Suspend
Resume
4109E–8051–06/03
The Suspend state can be detected by the USB controller if all the clocks are enabled
and if the USB controller is enabled. The bit SPINT is set by hardware when an idle
state is detected for more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can stop the clocks and put the
C51 in Idle or Power-down mode. The Resume detection is still active.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS-
2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
When the USB controller is in Suspend state, the Resume detection is active even if all
the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit
is set by hardware when a non-idle state occurs on the USB bus. This triggers an inter-
rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and
the interrupt function is then executed. The firmware should first enable the 48 MHz
generation and then reset to 0 the SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB
operation in order to wake up the USB controller from its Suspend mode.
The USB controller is then re-activated.
Figure 66. Example of a Suspend/Resume management
PCLK bit in the USBCON register.
Detection of a SUSPEND State
Detection of a RESUME State
WUPCPU
SPINT
Microcontroller in Power-down
Clear WUPCPU Bit
USB Controller Init
Clear SUSPCLK
Clear SPINT Bit
Set SUSPCLK
Disable PLL
Enable PLL
AT8xC51SND1C
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