MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 60

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

Configuration and Mask Option
5.3 Functional Description
Technical Data
60
† One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
# Non-volatile FLASH register; write by programming.
$FFD0
Addr.
$001E
$001F
Configuration Register 2
Configuration Register 1
Mask Option Register
Register Name
NOTE:
(CONFIG2)
(CONFIG1)
(MOR)
Configuration and Mask Option Registers (CONFIG & MOR)
†
†
#
The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration
registers are located at $001E and $001F. The configuration registers
may be read at anytime.
The options except LVIT[1:0] are one-time writable by the user after
each reset. The LVIT[1:0] bits are one-time writable by the user only after
each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in
The mask option register (MOR) is used to select the oscillator option for
the MCU: crystal oscillator or RC oscillator. The MOR is implemented as
a byte in FLASH memory. Hence, writing to the MOR requires
programming the byte.
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 5-1. CONFIG Registers Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
OSCSEL
IRQPUD
COPRS
Bit 7
R
0
0
Go to: www.freescale.com
= Reserved
R
R
R
6
0
0
R
R
R
5
0
0
Unaffected by reset; $FF when blank
LVIT1
LVID
0*
R
4
0
Figure 5-2
LVIT0
0*
R
R
3
0
and
SSREC
MC68HC908JL8
R
R
2
0
0
Figure 5-3.
STOP
R
R
1
0
0
MOTOROLA
—
ICLKDIS
Rev. 2.0
STOP_
COPD
Bit 0
R
0
0