ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 120
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ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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Definitions
Timer/Counter Clock
Sources
Counter Unit
120
ATmega640/1280/1281/2560/2561
Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 121. for details.
The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which
can be used to generate an Output Compare interrupt request.
Many register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the
Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when
using the register or bit defines in a program, the precise form must be used, i.e.,
TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 72 are also used extensively throughout the document.
Table 72. Definitions
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select
(CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on
clock sources and prescaler, see “Timer/Counter 0, 1, 3, 4, and 5 Prescaler” on page
172.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 38 shows a block diagram of the counter and its surroundings.
Figure 38. Counter Unit Block Diagram
Signal description (internal signals):
BOTTOM
MAX
TOP
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNTn
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The
assignment is dependent on the mode of operation.
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
direction
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
T0
in the following.
Clock Select
( From Prescaler )
Detector
Edge
2549K–AVR–01/07
Tn
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