ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 164
ATMEGA2561V
Manufacturer Part Number
ATMEGA2561V
Description
8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA2561V.pdf
(449 pages)
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TCCR1C – Timer/Counter 1
Control Register C
TCCR3C – Timer/Counter 3
Control Register C
TCCR4C – Timer/Counter 4
Control Register C
TCCR5C – Timer/Counter 5
Control Register C
164
ATmega640/1280/1281/2560/2561
•
•
•
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a
non-PWM mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an
immediate compare match is forced on the waveform generation unit. The
OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that
the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value
present in the COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer
in Clear Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
•
These bits are reserved for future use. For ensuring compatibility with future devices,
these bits must be written to zero when TCCRnC is written.
Bit
(0x82)
Read/Write
Initial Value
Bit
(0x92)
Read/Write
Initial Value
Bit
(0xA2)
Read/Write
Initial Value
Bit
(0x122)
Read/Write
Initial Value
Bit 7 – FOCnA: Force Output Compare for Channel A
Bit 6 – FOCnB: Force Output Compare for Channel B
Bit 5 – FOCnC: Force Output Compare for Channel C
Bit 4:0 – Reserved Bits
FOC1A
FOC3A
FOC4A
FOC5A
W
W
W
W
7
0
7
0
7
0
7
0
FOC1B
FOC3B
FOC4B
FOC5B
W
W
W
W
6
0
6
0
6
0
6
0
FOC1C
FOC3C
FOC4C
FOC3C
W
W
W
W
5
0
5
0
5
0
5
0
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
R
R
R
R
3
–
0
3
–
0
3
–
0
3
–
0
R
R
R
R
2
–
0
2
–
0
2
–
0
2
–
0
R
R
R
R
1
–
0
1
–
0
1
–
0
1
–
0
R
R
R
R
0
–
0
0
–
0
0
–
0
0
–
0
2549K–AVR–01/07
TCCR1C
TCCR3C
TCCR4C
TCCR5C
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