ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 157

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Timer/Counter Timing
Diagrams
2549K–AVR–01/07
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating
a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set, and when the OCRnx Register is updated with the
OCRnx buffer value (only for modes utilizing double buffering). Figure 57 shows a timing
diagram for the setting of OCFnx.
Figure 57. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
Figure 58 shows the same timing data, but with the prescaler enabled.
Figure 58. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
Figure 59 shows the count sequence close to TOP in various modes. When using phase
and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The
timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
TCNTn
OCRnx
OCFnx
OCRnx
(clk
TCNTn
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
OCRnx - 1
OCRnx - 1
ATmega640/1280/1281/2560/2561
OCRnx
OCRnx
OCRnx Value
OCRnx Value
OCRnx + 1
OCRnx + 1
Tn
OCRnx + 2
OCRnx + 2
) is therefore
clk_I/O
157
/8)