ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 277

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Register Description
ADCSRB – ADC Control and
Status Register B
ACSR – Analog Comparator
Control and Status Register
2549K–AVR–01/07
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is
zero), the ADC multiplexer selects the negative input to the Analog Comparator. When
this bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-
ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on
page 276.
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off.
This bit can be set at any time to turn off the Analog Comparator. This will reduce power
consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-
ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt
can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the
Analog Comparator. When the bandgap reference is used as input to the Analog Com-
parator, it will take a certain time for the voltage to stabilize. If not stabilized, the first
conversion may give a wrong value. See “Internal Voltage Reference” on page 61.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to
ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode
defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if
the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Ana-
log Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
Bit
(0x7B)
Read/Write
Initial Value
Bit
0x30 (0x50)
Read/Write
Initial Value
ACD
R/W
R
7
0
7
–
0
ACBG
ACME
R/W
R/W
ATmega640/1280/1281/2560/2561
6
0
6
0
ACO
N/A
R
5
R
5
–
0
R/W
ACI
4
0
R
4
–
0
ACIE
MUX5
R/W
R/W
3
0
3
0
ADTS2
ACIC
R/W
R/W
2
0
2
0
ACIS1
ADTS1
R/W
R/W
1
0
1
0
ACIS0
ADTS0
R/W
R/W
0
0
0
0
ADCSRB
ACSR
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