ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 242

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

USART MSPIM Register
Description
UDRn – USART MSPIM I/O
Data Register
UCSRnA – USART MSPIM
Control and Status Register n
A
242
ATmega640/1280/1281/2560/2561
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDRn) in MSPI mode is
identical to normal USART operation. See “UDRn – USART I/O Data Register n” on
page 227.
•
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-
abled, the receive buffer will be flushed and consequently the RXCn bit will become
zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDRn). The
TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXCn Flag can generate a
Transmit Complete interrupt (see description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag
can generate a Data Register Empty interrupt (see description of the UDRIE bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnA is written.
Bit
Read/Write
Initial Value
RXCn
R/W
7
0
TXCn
R/W
6
0
UDREn
R/W
5
0
R
4
0
-
R
3
0
-
R
2
1
-
R
1
1
-
R
0
0
-
2549K–AVR–01/07
UCSRnA