ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 260

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

260
ATmega640/1280/1281/2560/2561
Figure 102. Data Transfer in Master Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be
written to one to transmit a START condition and TWINT must be set to clear the TWINT
Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as
soon as the bus becomes free. After a START condition has been transmitted, the
TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (See Table
118). In order to enter MR mode, SLA+R must be transmitted. This is done by writing
SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to
continue the transfer. This is accomplished by writing the following value to TWCR:
When SLA+R have been transmitted and an acknowledgement bit has been received,
TWINT is set again and a number of status codes in TWSR are possible. Possible sta-
tus codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken
for each of these status codes is detailed in Table 119. Received data can be read from
the TWDR Register when the TWINT Flag is set high by hardware. This scheme is
repeated until the last byte has been received. After the last byte has been received, the
MR should inform the ST by sending a NACK after the last received data byte. The
transfer is ended by generating a STOP condition or a repeated START condition. A
STOP condition is generated by writing the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access
the same Slave again, or a new Slave without transmitting a STOP condition. Repeated
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
TWINT
TWINT
TWINT
TWINT
1
1
1
1
Device 1
RECEIVER
MASTER
TWEA
TWEA
TWEA
TWEA
X
X
X
X
TRANSMITTER
Device 2
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
1
Device 3
TWSTO
TWSTO
TWSTO
TWSTO
0
0
1
0
........
TWWC
TWWC
TWWC
TWWC
X
X
X
X
Device n
V
CC
TWEN
TWEN
TWEN
TWEN
1
1
1
1
R1
–
0
–
0
–
0
–
0
R2
2549K–AVR–01/07
TWIE
TWIE
TWIE
TWIE
X
X
X
X