ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 306

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

On-chip Debug Specific
JTAG Instructions
PRIVATE0; 0x8
PRIVATE1; 0x9
PRIVATE2; 0xA
PRIVATE3; 0xB
Using the JTAG
Programming
Capabilities
Bibliography
306
ATmega640/1280/1281/2560/2561
The On-chip debug support is considered being private JTAG instructions, and distrib-
uted within ATMEL and to selected third party vendors only. Instruction opcodes are
listed for reference.
Private JTAG instruction for accessing On-chip debug system.
Private JTAG instruction for accessing On-chip debug system.
Private JTAG instruction for accessing On-chip debug system.
Private JTAG instruction for accessing On-chip debug system.
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS,
TDI, and TDO. These are the only pins that need to be controlled/observed to perform
JTAG programming (in addition to power pins). It is not required to apply 12V externally.
The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register must
be cleared to enable the JTAG Test Access Port.
The JTAG programming capability supports:
•
•
•
•
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or
LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a
chip erase. This is a security feature that ensures no back-door exists for reading out the
content of a secured device.
The details on programming through the JTAG interface and programming specific
JTAG instructions are given in the section “Programming via the JTAG Interface” on
page 361.
For more information about general Boundary-scan, the following literature can be
consulted:
•
•
Flash programming and verifying.
EEPROM programming and verifying.
Fuse programming and verifying.
Lock bit programming and verifying.
IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-
Wesley, 1992.
2549K–AVR–01/07