ATMEGA2561V ATMEL [ATMEL Corporation], ATMEGA2561V Datasheet - Page 206

• Manufacturer Part Number: ATMEGA2561V
• Description: 8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Register Description
SPCR – SPI Control Register
206
ATmega640/1280/1281/2560/2561
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the if the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable
any SPI operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 80 and Figure 81 for an example. The CPOL func-
tionality is summarized below:
Table 98. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 80 and Figure 81 for an example.
The CPOL functionality is summarized below:
Table 99. CPHA Functionality
Bit
0x2C (0x4C)
Read/Write
Initial Value
CPOL
CPHA
0
1
0
1
SPIE
R/W
7
0
SPE
R/W
6
0
DORD
R/W
5
0
Leading Edge
Leading Edge
Sample
MSTR
Falling
Rising
Setup
R/W
4
0
CPOL
R/W
3
0
CPHA
R/W
2
0
SPR1
R/W
1
0
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
SPR0
R/W
0
0
2549K–AVR–01/07
SPCR