LPC1752 PHILIPS [NXP Semiconductors], LPC1752 Datasheet

LPC1752

Manufacturer Part Number

LPC1752

Description

32-bit ARM Cortex-M3 MCU up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

Manufacturer

PHILIPS [NXP Semiconductors]

Datasheet

1.LPC1752.pdf (71 pages)

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Download datasheet (300Kb)

1. General description

2. Features

The LPC1758/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1758/56/54/52/51 operate at CPU frequencies of up to 100 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The peripheral complement of the LPC1758/56/54/52/51 includes up to 512 kB of ﬂash

memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,

8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,

SPI interface, 3 I

12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general

purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)

with separate battery supply, and up to 52 general purpose I/O pins.

LPC1758/56/54/52/51

32-bit ARM Cortex-M3 MCU; up to 512 kB ﬂash and 64 kB

SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

Rev. 02 — 11 February 2009

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory

Protection Unit (MPU) supporting eight regions is included.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

Up to 512 kB on-chip ﬂash programming memory. Enhanced ﬂash memory accelerator

enables high-speed 100 MHz operation with zero wait states.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

On-chip SRAM includes:

Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I

Digital-to-Analog converter peripherals, timer match signals, and for

memory-to-memory transfers.

Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance

CPU access.

Two/one 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA

memory, as well as for general purpose CPU instruction and data storage.

C-bus interfaces, 2-input plus 2-output I

S-bus, UART, the Analog-to-Digital and

S-bus interface, 6 channel

Objective data sheet

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