LPC1752 PHILIPS [NXP Semiconductors], LPC1752 Datasheet - Page 13

• Manufacturer Part Number: LPC1752
• Description: 32-bit ARM Cortex-M3 MCU up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
LPC1758_56_54_52_51_2
Objective data sheet
7.2 ARM Cortex-M3 processor
7.3 On-chip flash program memory
7.4 On-chip SRAM
7.5 Memory Protection Unit (MPU)
7.6 Memory map
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptable/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,
and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on official ARM website.
The LPC1758/56/54/52/51 contain up to 512 kB of on-chip flash memory. A new two-port
flash accelerator maximizes performance for use with the two fast AHB-Lite buses.
The LPC1758/56/54/52/51 contain a total of up to 64 kB on-chip static RAM memory. This
includes the main 32/16/8 kB SRAM, accessible by the CPU and DMA controller on a
higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a
separate slave port on the AHB multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
The LPC1758/56/54/52/51 have a Memory Protection Unit (MPU) which can be used to
improve the reliability of an embedded system by protecting critical data within the user
application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place.
The LPC1758/56/54/52/51 incorporate several distinct memory regions, shown in the
following figures.
user program viewpoint following reset. The interrupt vector area supports address
remapping.
Figure 3
Rev. 02 — 11 February 2009
shows the overall map of the entire address space from the
LPC1758/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2009. All rights reserved.
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