LPC1752 PHILIPS [NXP Semiconductors], LPC1752 Datasheet - Page 12

• Manufacturer Part Number: LPC1752
• Description: 32-bit ARM Cortex-M3 MCU up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
7. Functional description
LPC1758_56_54_52_51_2
Objective data sheet
Symbol
V
V
V
V
V
VREFP
VREFN
VBAT
SS
SSA
DD(3V3)
DD(REG)(3V3)
DDA
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
Pin description
7.1 Architectural overview
Pin
24, 33,
43, 57,
66, 78
9
21, 42,
56, 77
34, 67
8
10
12
16
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see
system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC1758/56/54/52/51 use a multi-layer AHB matrix to connect the ARM Cortex-M3
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
…continued
Type
I
I
I
I
I
I
I
I
Description
ground: 0 V reference.
analog ground: 0 V reference. This should nominally be the same voltage as V
but should be isolated to minimize noise and error.
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip
voltage regulator only.
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
power the ADC and DAC.
ADC positive reference voltage: This should be nominally the same voltage as
V
as a reference for ADC and DAC.
ADC negative reference voltage: This should be nominally the same voltage as
V
a reference for ADC and DAC.
RTC pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral.
DD(3V3)
DDA
SS
but should be isolated to minimize noise and error. Level on this pin is used as
but should be isolated to minimize noise and error. Level on this pin is used
Figure
Rev. 02 — 11 February 2009
but should be isolated to minimize noise and error. This voltage is used to
1). The I-code and D-code core buses are faster than the
LPC1758/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2009. All rights reserved.
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SS
,