LPC1752 PHILIPS [NXP Semiconductors], LPC1752 Datasheet - Page 23

• Manufacturer Part Number: LPC1752
• Description: 32-bit ARM Cortex-M3 MCU up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
LPC1758_56_54_52_51_2
Objective data sheet
7.18.1 Features
7.19.1 Features
7.19 I
7.20 I
The LPC1758/56/54/52/51 each contain three I
The I
(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
The I
and one word select signal. The basic I
master, and one slave. The I
channel, each of which can operate as either a master or a slave.
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C-bus serial I/O controllers
S-bus serial I/O controllers (LPC1758/56 only)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
2
2
2
2
C1 and I
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
S-bus provides a standard communication interface for digital audio applications.
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
2
C-bus controllers support multiple address recognition and a bus monitor mode.
2
C-bus can be used for test and diagnostic purposes.
2
C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
Rev. 02 — 11 February 2009
2
S-bus interface provides a separate transmit and receive
2
S connection has one master, which is always the
LPC1758/56/54/52/51
2
C-bus controllers.
32-bit ARM Cortex-M3 microcontroller
2
C is a multi-master bus and can be
© NXP B.V. 2009. All rights reserved.
2
C-bus).
23 of 71