SB82371 Intel Corporation, SB82371 Datasheet - Page 118

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
5.0.
5.1.
The test modes are decoded from the IRQ inputs (IRQ 7, 6, 5) and qualified with the TESTIN# pin. Test mode
selection is asynchronous. These signals need to remain in their respective state for the duration of the test
modes. The test modes are defined as follows.
5.2.
Tri-states all outputs and bi-directional buffers except for XDIR and DACK1#. Every output buffer except for
XDIR and DACK1# is configured as an input in NAND tree mode and included in the NAND chain. The first
input of the NAND chain is MDRQ1, and the NAND chain is routed counter-clockwise around the chip (e.g.,
MDRQ1, MDRQ0, MDAK1#, . . .). DACK1# is an intermediate output, and XDIR is the final output. PCICLK
and TESTIN# are the only input pins not included in the NAND chain. Note in the table above there are two
possible ways to select NAND tree test mode.
To perform a NAND tree test, all pins included in the NAND tree should be driven to 1 except for the following
pins, which use inverting Schmitt trigger inputs and should be driven to 0:
118
NAND Tree
NAND Tree
Tri-state All Outputs
Test Mode
TESTABILITY (PIIX/PIIX3)
Test Mode Description
NAND Tree Mode
Table 18. Perform NAND Tree Test (Pins Driven To 0)
IRQ7
0
x
1
Pin #
10
15
32
33
34
56
58
73
75
77
4
5
6
Table 17. Test Modes
IRQ6
x
x
1
Pin Name
ZEROWS#
IOCHK#
IRQ8#
IRQ10
IRQ11
IRQ12
IRQ1
IRQ9
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ5
0
1
x
TESTIN#
0
0
0