SB82371 Intel Corporation, SB82371 Datasheet - Page 39

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

2.2.13.
Address Offset :
Default Value:
Attribute:
These registers control the routing of motherboard device interrupts (MIRQ[1:0]) to the internal IRQ inputs of
the interrupt controller. Each MIRQx# can be independently routed to any one of 11 interrupts.
Note that, when an MIRQ line and a PIRQ# line are steered to the same ISA interrupt, the device connected
to the MIRQ line must be set for active high, level interrupts. In this case, the ISA interrupt will be masked. Bit
6 of that motherboard device IRQ Route Control Register must be programmed to a 0.
0
7
6
5
4
3:0
Bit
Bit
MBIRQ[1:0]—MOTHERBOARD DEVICE IRQ ROUTE CONTROL REGISTERS (Function 0)
Interrupt Routing Enable. 0=Enable routing; 1=Disable routing.
MIRQx/IRQx Sharing Enable. 0=Disable sharing; 1=Enable sharing. When sharing is
disabled and bit 7 of this register is 0, the interrupt specified by bits [3:0] is masked. Interrupt
sharing should only be enabled when the device connected to the MIRQ line and the device
connected to the ISA IRQ line both produce active high, level interrupts.
PIIX: Reserved
PIIX3: IRQ0 Enable, 1=Enable (IRQ0 Output), 0 = Disable (default, MIRQ0 input). When
enabled the MIRQ0/IRQ0 pin functions as the IRQ0 output and the IDE Interrupt Status flag in
Bus Master IDE Status Register is set by the IRQ15 input signal. When disabled the
MIRQ0/IRQ0 pin functions as the MIRQ0 input and the IDE Interrupt Status flag in the Bus
Master IDE Status Register is set by the MIRQ0 input signal.
Reserved. Read as zero.
Interrupt Routing. When bit 7=0, this field selects the routing of the MBIRQx to one of the
interrupt controller interrupt inputs.
Bits[3:0]
0000
0001
0010
0011
0100
0101
PIIX: ISA Clock Divisor Status RO. This bit reports the strapping option on the SYSCLK
signal. 1=clock divisor of 3 (PCICLK=25 MHz). 0=Clock divisor of 4 (PCICLK=33 MHz). Note
that, for PCICLK=30 MHz, a clock divisor of 4 must be selected and produces a SYSCLK of
7.5 MHz.
PIIX3: ISA Clock Divisor R/W. This bit controls the frequency of the SYSCLK signal.
1=clock divisor of 3 (PCICLK=25 MHz). 0=Clock divisor of 4 (PCICLK=33 MHz). Note that, for
PCICLK=30 MHz, a clock divisor of 4 must be selected and produces a SYSCLK of 7.5 MHz.
The default value of this bit is determined by the strapping option on the SYSCLK signal.
70h—MBIRQ0 (PIIX and PIIX3)
71h—MBIRQ1 (PIIX only)
80h
R/W
IRQ Routing
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5
Bits[3:0]
0110
0111
1000
1001
1010
Description
IRQ Routing
IRQ6
IRQ7
Reserved
IRQ9
IRQ10
Description
82371FB (PIIX) AND 82371SB (PIIX3)
Bits[3:0]
1011
1100
1101
1110
1111
IRQ Routing
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
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