SB82371 Intel Corporation, SB82371 Datasheet - Page 38

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
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6
5
4
3
2
1
Bit
PIIX: Reserved.
PIIX3: EXTSMI# Mode Enable (ESMIME)
used to enable a special SERR# handling protocol between the host-to-PCI bridge and the
PIIX3. When ESMIME is enabled, the operating mode of the EXTSMI# signal is determined
by the duration of the EXTSMI# signal. If the EXTSMI# signal is asserted for one PCLK, an
SERR# is reported in the NMISC Register (address 61h) and an NMI is generated, if enabled
in the NMI Registers (address 61h and 70h). If EXTSMI# is asserted for more than one
PCLK, the standard mode for handling EXTSMI# is used (i.e., same as when this bit is set to
0).
When disabled (standard mode) and a falling edge is detected on EXTSMI#, an SMI is
signaled, if EXTSMI# signaling is enabled.
Reserved.
PIIX: Reserved.
PIIX3: USB Enable (USBE)
functionality is disabled. This bit must be set to 1 to access function 2 configuration space.
Note that dynamically disabling USB is not supported in PIIX3. This bit is used to
enable/disable the USB at boot time. In case software has to disable the USB during run time
it has to do the following: Software must turn off the master enable and I/O Decode Enable
for function 2 (via the PCICMD Register, function 2) prior to writing this bit to 0.
Reserved.
PIIX: PCI Header Type Bit Enable R/W. This bit controls the Header Type Bit in the PIIX
register 0Eh which defines the PIIX as a multifunction device. This bit defaults to 1
(Multifunction device) and should be left in the default state.
PIIX3: Reserved.
PIIX: Internal ISA DMA or External DMA Mode Status (IEDMAS)
Operation. This bit reports the strapping option selected on the TC signal (pulled high at reset
for a value of 0).
PIIX3: Reserved,
Gate not necessary
if system EXTSMI#
is not used
R/W. 1=Enable. 0=Disable (default). When disabled, all USB
Host-to-PCI
Bridge
SERR#
PIIX3
Description
EXTSMI#
R/W. 1=Enable. 0=Disable (default). This bit is
System EXTSMI#
(Assumes minimum
assertion of more
than one PCLK)
SMI_NMI.drw
RO. 0=Normal DMA