SB82371 Intel Corporation, SB82371 Datasheet - Page 60

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
60
5
4
3
2
1
0
Bit
A20Gate Pass-through Enable (A20PTEN) R/W. 1=Enable A20GATE pass-through
sequence. 0=Disable (default). When enabled, the logic will pass-through the following
A20GATE command sequence:
Cycle
Write
Write
Read
Write
Any deviation in the above sequence causes the host controller to immediately exit the
sequence and return to standard operation, performing an I/O trap and generating an SMI# if
appropriate enable bits are set.
When enabled, SMI# is not generated during the sequence, even if the various enable bits are
set. Note that during a pass-through sequence, the above status bits are not set for the I/O
accesses that are part of the sequence.
Trap/SMI ON IRQ Enable (USBSMIEN) R/W. 1=Enable SMI# generation on USB IRQ.
0=Disable (default).
Trap/SMI On 64h Write Enable (64WEN) R/W. 1=Enable I/O Trap and SMI# generation on
port 64h write.
0=Disable (default).
Trap/SMI On 64h Read Enable (64REN) R/W. 1=Enable I/O Trap and SMI# generation on
port 64h read.
0=Disable (default).
Trap/SMI On 60h Write Enable (60WEN) R/W. 1=Enable I/O Trap and SMI# generation on
port 60h write.
0=Disable (default).
Trap/SMI On 60h Read Enable (60REN) R/W. 1 = Enable I/O Trap and SMI# generation on
port 60h read.
0=Disable (default).
Address
64h
60h
64h
64h
Data
D1h
xxh
FFh
N/A
( 0 or more)
( 1 or more) (Starts the Sequence)
( Standard End of A20GATE Pass-through Sequence)
Description