SB82371 Intel Corporation, SB82371 Datasheet - Page 4

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

82371FB (PIIX) AND 82371SB (PIIX3)
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2.3. PCI Configuration Registers—IDE Interface (Function 1) ................................................................... 47
2.4. PCI Configuration Registers Universal Serial Bus (Function 2) (PIIX3 Only).................................... 53
2.5. ISA-Compatible Registers .................................................................................................................. 61
2.2.19. SMIEN—SMI ENABLE REGISTER (Function 0) ....................................................................... 43
2.2.20. SEE—SYSTEM EVENT ENABLE REGISTER (Function 0) ...................................................... 44
2.2.21. FTMR—FAST OFF TIMER REGISTER (Function 0)................................................................. 45
2.2.22. SMIREQ—SMI REQUEST REGISTER (Function 0) ................................................................. 45
2.2.23. CTLTMR—CLOCK SCALE STPCLK# LOW TIMER (Function 0) .............................................. 46
2.2.24. CTHTMR—CLOCK SCALE STPCLK# HIGH TIMER (Function 0)............................................. 47
2.3.1. VID—Vendor Identification Register (Function 1) ........................................................................ 47
2.3.2. DID—DEVICE IDENTIFICATION REGISTER (Function 1) ......................................................... 47
2.3.3. PCICMD—COMMAND REGISTER (Function 1) ......................................................................... 48
2.3.4. PCISTS—PCI DEVICE STATUS REGISTER (Function 1) .......................................................... 48
2.3.5. RID—REVISION IDENTIFICATION REGISTER (Function 1)...................................................... 49
2.3.6. CLASSC CLASS CODE REGISTER (Function 1)..................................................................... 49
2.3.7. MLT—MASTER LATENCY TIMER REGISTER (Function 1) ...................................................... 49
2.3.8. HEDT—HEADER TYPE REGISTER (Function 1) ....................................................................... 50
2.3.9. BMIBA—BUS MASTER INTERFACE BASE ADDRESS REGISTER (Function 1) ...................... 50
2.3.10. IDETIM—IDE TIMING REGISTER (Function 1) ........................................................................ 51
2.3.11. SIDETIM—SLAVE IDE TIMING REGISTER (Function 1) (PIIX3 Only) ..................................... 52
2.4.1. VID—VENDOR IDENTIFICATION REGISTER (Function 2) (PIIX3)............................................ 53
2.4.2. DID DEVICE IDENTIFICATION REGISTER (Function 2) (PIIX3) ............................................. 54
2.4.3. PCICMD COMMAND REGISTER (Function 2) (PIIX3) ............................................................. 54
2.4.4. DS DEVICE STATUS REGISTER (Function 2) (PIIX3)............................................................. 55
2.4.5. RID REVISION IDENTIFICATION REGISTER (Function 2) (PIIX3).......................................... 55
2.4.6. CLASSC CLASS CODE REGISTER (Function 2) (PIIX3)......................................................... 56
2.4.7. MLT MASTER LATENCY TIMER REGISTER (Function 2) (PIIX3) .......................................... 56
2.4.8. HEDT HEADER TYPE REGISTER (Function 2) (PIIX3) ........................................................... 57
2.4.9. BASEADD
2.4.10. IL Interrupt Line Register (Function 2) (PIIX3)......................................................................... 57
2.4.11. INTRP INTERRUPT PIN (Function 2) (PIIX3) ......................................................................... 58
2.4.12. SBRNUM SERIAL BUS RELEASE NUMBER (Function 2) (PIIX3) ......................................... 58
2.4.13. MSTAT MISCELLANEOUS STATUS REGISTER (Function 2) (PIIX3)................................... 58
2.4.14. LEGSUP LEGACY SUPPORT REGISTER (FUNCTION 2) (PIIX3) ........................................ 59
2.5.1. DMA REGISTERS....................................................................................................................... 61
2.5.1.1. DCOM—DMA Command Register........................................................................................ 61
2.5.1.2. DCM—DMA Channel Mode Register.................................................................................... 61
2.5.1.3. DR—DMA Request Register................................................................................................. 62
2.5.1.4. Mask Register—Write Single Mask Bit ................................................................................. 63
2.5.1.5. Mask Register—Write All Mask Bits...................................................................................... 63
2.5.1.6. DS—DMA Status Register.................................................................................................... 64
2.5.1.7. DMA Base And Current Address Registers (8237 Compatible Segment).............................. 64
2.5.1.8. DMA Base And Current Byte/Word Count Registers (Compatible Segment) ........................ 65
I/O SPACE BASE ADDRESS (Function 2) (PIIX3) ................................................ 57