SB82371 Intel Corporation, SB82371 Datasheet - Page 31

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

2.2.
2.2.1.
Address Offset:
Default Value:
Attribute:
The VID Register contains the vendor identification number. This register, along with the Device Identification
Register, uniquely identifies any PCI device. Writes to this register have no effect.
2.2.2.
Address Offset:
Default Value:
Attribute:
The DID Register contains the device identification number. This register, along with the VID Register, define
the PIIX. Writes to this register have no effect.
2.2.3.
Address Offset:
Default Value:
Attribute:
This 16-bit register provides basic control over the PIIX's ability to respond to PCI cycles.
15:10
9
8
7:5
4
3
15:0
15:0
Bit
Bit
Bit
PCI Configuration Registers—PCI To ISA Bridge (Function 0)
VID—VENDOR IDENTIFICATION REGISTER (Function 0)
DID—DEVICE IDENTIFICATION REGISTER (Function 0)
PCICMD—COMMAND REGISTER (Function 0)
Vendor Identification Number. This is a 16-bit value assigned to Intel.
Device Identification Number. This is a 16-bit value assigned to the PIIX.
Reserved. Read as 0.
Fast Back-to-Back Enable. (Not Implemented) This bit is hardwired to 0.
PIIX: Reserved. Read as 0.
PIIX3: SERR# Enable (SERRE). 1=Enable. 0=Disable. When enabled (and bit 3=1 in the
DLC register), a delayed transaction timeout causes the PIIX3 to assert the SERR# signal.
The PCISTS register reports the status of the SERR# signal.
Reserved. Read as 0.
Postable Memory Write Enable. (Not Implemented) This bit is hardwired to 0.
Special Cycle Enable (SCE). 1=Enable, the PIIX/PIIX3 recognizes shutdown special cycle.
0=Disable, the PIIX/PIIX3 ignores all PCI Special Cycles.
00–01h
8086h
Read Only
02–03h
122Eh
7000h
Read Only
04–05h
0007h
Read/Write
(PIIX)
(PIIX3)
Description
Description
Description
82371FB (PIIX) AND 82371SB (PIIX3)
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