SB82371 Intel Corporation, SB82371 Datasheet - Page 49

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

2.3.5.
Address Offset:
Default Value:
Attribute:
This 8 bit register contains device stepping information. Writes to this register have no effect.
2.3.6.
Address Offset:
Default Value:
Attribute:
This register contains the device programming interface information related to the Sub-Class Code and Base
Class Code definition for the PIIX3 (function 1). This register also identifies the Base Class Code and the
function sub-class in relation to the Base Class Code.
2.3.7.
Address Offset:
Default Value:
Attribute:
MLT controls the amount of time PIIX, as a bus master, can burst data on the PCI Bus. The count value is an
8-bit quantity. However, MLT[3:0] are reserved and 0 when determining the count value. MLT is cleared and
suspended when PIIX/PIIX3 is not asserting FRAME#. When PIIX/PIIX3 asserts FRAME#, the counter
begins counting. If the PIIX/PIIX3 finishes its transaction before the count expires, the MLT count is ignored.
If the count expires before the transaction completes (count = # of clocks programmed in MLT), PIIX/PIIX3
initiates a transaction termination as soon as its PHLDA# is removed. The number of clocks programmed in
the MLT represents the guaranteed time slice (measured in PCI clocks) allotted to PIIX. The default value of
MLT is 00h or 0 PCI clocks.
8
7
6:0
7:0
23:1
6
15:8
7:0
Bit
Bit
Bit
RID—REVISION IDENTIFICATION REGISTER (Function 1)
CLASSC CLASS CODE REGISTER (Function 1)
MLT—MASTER LATENCY TIMER REGISTER (Function 1)
Data Parity Detected (DPD). (Not Implemented) Read as 0.
Fast Back to back Capable (FBC)—RO. Hardwired to 1. This bit indicates to the PCI Master
that PIIX, as a target, is capable of accepting fast back-to-back transactions.
Reserved. Read as 0’s.
Revision ID Byte. The register is hardwired to the default value during manufacturing.
Base Class Code (BASEC). 01h=Mass storage device.
Sub-Class Code (SCC). 01h=IDE controller.
Programming Interface (PI). 80h=Capable of IDE bus master operation.
08h
Refer to applicable specification update document
Read Only
09 0Bh
010180h
Read Only
0Dh
00h
Read / Write
Description
Description
Description
82371FB (PIIX) AND 82371SB (PIIX3)
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