SB82371 Intel Corporation, SB82371 Datasheet - Page 67

• Manufacturer Part Number: SB82371
• Description: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
• Manufacturer: Intel Corporation

coded decimal (BCD) format. After writing the control word, a new count can be written at any time. The new
value takes effect according to the programmed mode.
Read Back Command
The Read Back Command is used to determine the count value, programmed mode, and current states of the
OUT pin and Null count flag of the selected counter or counters. The Read Back Command is written to the
Timer Control Word Register which latches the current states of the above mentioned variables. The value of
the counter and its status may then be read by I/O access to the counter address. Note that The Timer
Counter Register bit definitions are different during the Read Back Command than for a normal Timer
Counter Register write.
7:6
5:4
3:1
0
7:6
5
4
Bit
Bit
Counter Select. The Read Back Command is selected when bits[7:6] are both 1.
Bit[7:6]
00
01
10
11
Read/Write Select. The Counter Latch Command is selected when bits[5:4] are both 0.
Bit[5:4]
00
01
10
11
Counter Mode Selection. Bits [3:1] select one of six possible counter modes.
Bit[3:1]
000
001
X10
X11
100
101
Binary/BCD Countdown Select. 0=Binary countdown. The largest possible binary count is
2 16 . 1=Bbinary coded decimal (BCD) count is used. The largest BCD count allowed is 10 4 .
Read Back Command. When bits[7:6]=11, the Read Back Command is selected during a
write to the Timer Control Word Register. Following the Read Back Command, I/O reads from
the selected counter’s I/O addresses produce the current latch status, the current latched
count, or both if bits 4 and 5 are both 0.
Latch Count of Selected Counters. When bit 5=0, the current count value of the selected
counters will be latched. When bit 5=1, the count will not be latched.
Latch Status of Selected Counters. When bit 4=0, the status of the selected counters will be
latched. When bit 4=1, the status will not be latched. The status byte format is described in
Section 4.3.3, Interval Timer Status Byte Format Register.
Mode
0
1
2
3
4
5
Function
Counter 0 select
Counter 1 select
Counter 2 select
Read Back Command
Function
Counter Latch Command
R/W Least Significant Byte
R/W Most Significant Byte
R/W LSB then MSB
Function
Out signal on end of count (=0)
Hardware retriggerable one-shot
Rate generator (divide by n counter)
Square wave output
Software triggered strobe
Hardware triggered strobe
Description
Description
82371FB (PIIX) AND 82371SB (PIIX3)
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