AM79C973VCW AMD [Advanced Micro Devices], AM79C973VCW Datasheet
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AM79C973VCW
Manufacturer Part Number
AM79C973VCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C973VCW.pdf
(304 pages)
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Am79C973/Am79C975
PCnet™-FAST III
Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
DISTINCTIVE CHARACTERISTICS
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Single-chip PCI-to-Wire Fast Ethernet controller
— 32-bit glueless PCI host interface
— Supports PCI clock frequency from DC to
— Supports network operation with PCI clock
— High performance bus mastering
— PCI specification revision 2.2 compliant
— Supports PCI Subsystem/Subvendor ID/
— Supports both PCI 5.0 V and 3.3 V signaling
— Plug and Play compatible
— Big endian and little endian byte alignments
Fully Integrated 10/100 Mbps Physical Layer
Interface (PHY)
— Conforms to IEEE 802.3 standard for
— Integrated 10BASE-T transceiver with on-
— Fully integrated MLT-3 encoder/decoder for
— Provides a PECL interface for 100BASE-FX
— Full-duplex capability for 10BASE-T and
— IEEE 802.3u Auto-Negotiation between 10
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
33 MHz independent of network clock
from 15 MHz to 33 MHz
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
Vendor ID programming through the
EEPROM interface
environments
supported
10BASE-T, 100BASE-TX, and 100BASE-FX
interfaces
chip filtering
100BASE-TX
fiber implementations
100BASE-TX
Mbps and 100 Mbps, half- and full-duplex op-
eration
PRELIMINARY
R f
t AMD’ W b it (
d
) f
Supports PC98/PC99 and Wired for
Management baseline specifications
— Full OnNow support including pattern
— Implements AMD’s patented Magic Packet™
— Magic Packet mode and the physical address
— Supports PCI Bus Power Management
— Supports Advanced Configuration and
— Supports Network Device Class Power
Serial Management Interface enables remote
alerting of system management events
— Inter-IC (I
— System Management Bus (SMBus)
— Optional interrupt pin simplifies software
Large independent internal TX and RX FIFOs
— Programmable FIFO watermarks for both TX
— RX frame queuing for high latency PCI bus
— Programmable allocation of buffer space
EEPROM interface supports jumperless design
and provides through-chip programming
— Supports extensive programmability of
Supports up to 1 megabyte (Mbyte) optional
Boot PROM and Flash for diskless node
application
Extensive programmable internal/external
loopback capabilities
Extensive programmable LED status support
th l t t i f
matching and link status wake-up events
technology for remote wake-up & power-on
loaded from EEPROM at power up without
requiring PCI clock
Interface Specification Revision 1.1
Power Interface (ACPI) Specification Version
1.0
Management Specification Version 1.0a
compliant signaling interface and register
access protocol
interface
and RX operations
host operation
between RX and TX queues
device operation through EEPROM mapping
2
C) compliant electrical interface
Publication# 21510
Issue Date: August 2000
ti
Rev: E Amendment/0
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