AM79C973VCW AMD [Advanced Micro Devices], AM79C973VCW Datasheet - Page 294
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AM79C973VCW
Manufacturer Part Number
AM79C973VCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C973VCW.pdf
(304 pages)
- Current page: 294 of 304
- Download datasheet (3Mb)
INDEX
Numerics
10 Mbps Receive (RX±) Timing
10 Mbps Transmit (TX±) Timing
10/100 Media Access Control . . . . . . . . . . .70
10/100 PHY Unit Overview . . . . . . . . . . . .79
100BASE-FX (Fiber Interface) . . . . . . . . . .79
100BASE-X Physical Layer . . . . . . . . . . . .79
100BASE-X Transmit and Receive
10BASE-T Block . . . . . . . . . . . . . . . . . . . . .86
10BASE-T Physical Layer . . . . . . . . . . . . . .79
EBDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Expansion Bus Data/Address . . . . . . . . . . . .34
16-Bit Software Model . . . . . . . . . . . . . . . .66
C/BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
TXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
32-Bit Software Model . . . . . . . . . . . . . . . .67
EBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
EBUA_EBA . . . . . . . . . . . . . . . . . . . . . . . . .33
Expansion Bus Data . . . . . . . . . . . . . . . . . . .34
Expansion Bus Upper
A
Absolute Maximum Ratings . . . . . . .224, 266
Address and Data . . . . . . . . . . . . . . . . . . . . .29
Address Match Logic . . . . . . . . . . . . . . . . .205
Address Matching . . . . . . . . . . . . . . . . . . . .75
Address Parity Error Response . . . . . . . . . .45
Address PROM Space . . . . . . . . . . . . . . . .109
Address Strobe/Expansion Bus
Advanced Parity Error Handling . . . . . . . . .56
Alternative Method for Initialization . . . . .283
Am79C972 Bus Configuration
Am79C972 Programmable Registers . . . .220
Am79C973 EEPROM Map . . . . . . . . . . . .100
Am79C975 EEPROM Map . . . . . . . . . . . .101
Am79C975 PIN DESIGNATIONS . . . . . .245
AMD Flash Programming . . . . . . . . . . . . . .95
294
Diagram . . . . . . . . . . . . . . . . . . . . . . . . .233
Diagram . . . . . . . . . . . . . . . . . . . . . . . . .233
Data Paths of the Internal PHY . . . . . . . . .81
Address/ Expansion Bus Address . . . . . . .33
Output Enable . . . . . . . . . . . . . . . . . . . . . .34
Registers . . . . . . . . . . . . . . . . . . . . . . . . .222
P R E L I M I N A R Y
Am79C973/Am79C975
An Alternative LAPP Flow
APDW Values . . . . . . . . . . . . . . . . . . . . . .186
APP 3 Buffer Grouping for
AS_EBOE . . . . . . . . . . . . . . . . . . . . . . . . . .34
Automatic EEPROM Read Operation . . . . .98
Automatic Network Port Selection . . . . . .271
Automatic Network Selection
Automatic Pad Generation . . . . . . . . . . . . . .74
Automatic Pad Stripping . . . . . . . . . . . . . . .76
Automatic PREAD EEPROM Timing . . .238
Auto-Negotiation . . . . . . . . . . . . . . . . .87, 271
Auto-Negotiation Advertisement
Auto-Negotiation Capabilities . . . . . . .88, 271
Auto-Negotiation Link Partner Ability
Auto-Poll External PHY Status Polling . . .270
Auxiliary Power . . . . . . . . . . . . . . . . . . . . .102
B
Basic Burst Read Transfer . . . . . . . . . . . . . .47
Basic Burst Write Transfer . . . . . . . . . . . . .49
BASIC FUNCTIONS . . . . . . . . . . . . . . . . .39
Basic Non-Burst Read Transfer . . . . . . . . . .47
Basic Non-Burst Write Transfer . . . . . . . . .49
Basic Operation . . . . . . . . . . . . . . . . . . . . .246
BCR Registers . . . . . . . . . . . . . . . . . .159, 161
BCR0
BCR1
BCR16
BCR19
BCR20
BCR28
Two-interrupt Method . . . . . . . . . . . . . .293
Register (Register 4) . . . . . . . . . . . . . . . .276
Register (Register 5) . . . . . . . . . . . . . . . .277
Two-Interrupt Method . . . . . . . . . . . . .291
Exceptions . . . . . . . . . . . . . . . . . . . . . .271
External PHY Auto-Negotiable . . . . . .272
External PHY Not Auto-Negotiable . .271
Force External Reset . . . . . . . . . . . . . .272
Master Mode Read Active . . . . . . . . . .157
Master Mode Write Active . . . . . . . . .158
I/O Base Address Lower . . . . . . . . . . .172
EEPROM Control and Status . . . . . . .175
Software Style . . . . . . . . . . . . . . . . . . .178
Expansion Bus Port Address Lower
(Used for Flash/EPROM and
SRAM Accesses) . . . . . . . . . . . . . .183
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