AM79C973VCW AMD [Advanced Micro Devices], AM79C973VCW Datasheet - Page 77
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AM79C973VCW
Manufacturer Part Number
AM79C973VCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C973VCW.pdf
(304 pages)
- Current page: 77 of 304
- Download datasheet (3Mb)
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the ISO 8802-
3 (IEEE/ANSI 802.3) definition) contained in the frame.
The length indicates the actual number of LLC data
bytes contained in the message. Any received frame
which contains a length field less than 46 bytes will have
Since any valid Ethernet Type field value will always be
greater than a normal IEEE 802.3 Length field (Š46),
the Am79C973/Am79C975 controller will not attempt to
strip valid Ethernet frames. Note that for some network
protocols, the value passed in the Ethernet Type and/
or IEEE 802.3 Length field is not compliant with either
standard and may cause problems if pad stripping is
enabled.
Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the Am79C973/Am79C975
controller. Note that if the Automatic Pad Stripping fea-
ture is enabled, the FCS for padded frames will be ver-
ified against the value computed for the incoming bit
stream including pad characters, but the FCS value for
a padded frame will not be passed to the host. If an
FCS error is detected in any frame, the error will be re-
ported in the CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories, i.e., those conditions which are the
Increasing Time
1010....1010
Preamble
Start of Frame
at Time = 0
Bits
56
Figure 34. IEEE 802.3 Frame And Length Field Transmission Order
10101011
SFD
Bits
8
Destination
Address
Bytes
6
P R E L I M I N A R Y
Am79C973/Am79C975
Bit
0
Address
Source
Bytes
Significant
6
Most
Byte
the pad field stripped (if ASTRP_RCV is set). Receive
frames which have a length field of 46 bytes or greater
will be passed to the host unmodified.
Figure 34 shows the byte/bit ordering of the received
length field for an IEEE 802.3-compatible frame format.
result of normal network operation, and those which
occur due to abnormal network and/or host related
events.
Normal events which may occur and which are handled
autonomously by the Am79C973/Am79C975 controller
are basically collisions within the slot time and auto-
m at i c r u nt p a cke t r ej e c t i o n. T he A m7 9 C 97 3 /
Am79C975 controller will ensure that collisions that
occur within 512 bit times from the start of reception
(excluding preamble) will be automatically deleted from
the receive FIFO with no host intervention. The receive
FIFO will delete any frame that is composed of fewer
than 64 bytes provided that the Runt Packet Accept
(RPA bit in CSR124) feature has not been enabled and
the network interface is operating in half-duplex mode,
or the full-duplex Runt Packet Accept Disable bit (FDR-
PAD, BCR9, bit 2) is set. This criterion will be met re-
gardless of whether the receive frame was the first (or
only) frame in the FIFO or if the receive frame was
queued behind a previously received message.
Abnormal network conditions include:
Bit
Length
7
Bytes
2
Bit
0
Significant
1 – 1500
Bytes
Least
Data
Byte
LLC
46 – 1500
Bytes
Bit
7
45 – 0
Bytes
Pad
Bytes
FCS
4
21510D-39
77
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