S71GL064A08 SPANSION [SPANSION], S71GL064A08 Datasheet
S71GL064A08
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S71GL064A08 Summary of contents
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S71GL064A Based MCPs Stacked Multi-Chip Product (MCP) Flash Memory and RAM 64 Megabit ( 16-bit) CMOS 3.0 Volt-only Page Mode Flash Memory and 16/8 Megabit (1M/512K x 16-bit) Pseudo Static RAM / Static RAM Notice to Readers: The ...
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... Information, Preliminary, or Full Production. See the section “Notice on Data Sheet Designations” for definitions. Packages — 1 ball FBGA (TLC056) Operating Temperature — –25°C to +85°C — –40°C to +85°C Flash Memory Density 64Mb 8Mb S71GL064A80/S71GL064A08 16Mb S71GL064AA0/S71GL064A0A Revision A Amendment 2 Issue Date February 8, 2005 ADVANCE INFORMATION ...
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Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, in- cluding development, qualification, initial production, and full production. In ...
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... Product Selector Guide 64 Mb Flash Memory Device-Model# (Note) Flash Access time (ns) S71GL064A80-0K S71GL064A80-0P S71GL064A08-0B S71GL064A08-0F S71GL064AA0-0K 100 S71GL064AA0-0P S71GL064AA0-0U S71GL064AA0-0Z S71GL064A0A-0B S71GL064A0A-0F Note: Please see the valid combinations table for the model# description. February 8, 2005 S71GL064A_00_A2 ...
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S71GL064A based MCPs Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1 MCP Features ........................................................................................................ 1 General Description . . . . . . . . . ...
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Table 13. 4Mb pSRAM Asynchronous .................................... 76 Table 14. 8Mb pSRAM Asynchronous .................................... 76 Table 15. 16Mb pSRAM Asynchronous .................................. 77 Table 16. 16Mb pSRAM Page Mode ...................................... 78 Table 17. 32Mb pSRAM ...
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Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 59. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=V , CS2=WE#=V , ...
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MCP Block Diagram CE1#f WP#/ACC RESET# Flash-only Address Shared Address OE# WE# CE1#s UB# LB# CE2s February 8, 2005 S71GL064A_00_A2 ...
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... MCP S71GL064AA0 S71GL064A0A S71GL064A80 S71GL064A08 Special Handling Instructions For FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is ex- posed to temperatures above 150° ...
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Pin Description A21–A0 DQ15–DQ0 CE1#f CE1#s CE2s OE# WE# RY/BY# UB# LB# RESET# WP#/ACC CCS Logic Symbol February 8, 2005 S71GL064A_00_A2 ...
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Ordering Information The order number is formed by a valid combinations of the following: S71GL 064 Table ...
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... BAW S71GL064AA0 S71GL064AA0 S71GL064AA0 S71GL064A0A S71GL064A0A S71GL064A80 S71GL064A80 S71GL064A08 S71GL064A08 S71GL064AA0 BFW S71GL064AA0 S71GL064AA0 S71GL064AA0 S71GL064A0A S71GL064A0A S71GL064A80 S71GL064A80 S71GL064A08 S71GL064A08 S71GL064AA0 BAI S71GL064AA0 S71GL064AA0 S71GL064AA0 S71GL064A0A S71GL064A0A S71GL064A80 S71GL064A80 S71GL064A08 S71GL064A08 S71GL064AA0 BFI S71GL064AA0 S71GL064AA0 S71GL064AA0 S71GL064A0A S71GL064A0A Notes: 1. Type 0 is standard. Specify other options as required. ...
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Physical Dimensions TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA Package D 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 56X 0. 0.08 M ...
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S29GLxxxA MirrorBit™ Flash Family Stacked Multi-Chip Product (MCP) Flash Memory and RAM 64 Megabit ( 16-bit) CMOS 3.0 Volt-only Page Mode Flash Memory and 16/8 Megabit (1M/512K x 16-bit) Pseudo Static RAM / Static RAM Data Sheet Distinctive ...
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General Description The S29GL064A Mb, organized as 4,194,304 words or 8,388,608 bytes. Access times as fast are available. Note that each access time has a specific operat- ing voltage range (VCC) as specified in ...
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Product Selector Guide S29GL064A Part Number Speed Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (ns) Max. OE# Access Time (ns) February 8, 2005 S71GL064A_00_A2 I n ...
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Block Diagram RY/BY RESET# WE# State Control WP#/ACC Command Register CE# OE# V Detector CC A21– Sector ...
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Pin Descriptions A21–A0 A20–A0 DQ7–DQ0 DQ14–DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC ACC WP# RESET# RY/BY Logic Symbols S29GL064A (Models R1, R2) February 8, 2005 S71GL064A_00_A2 I ...
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S29GL064A (Models R3, R4) S29GL064A (Model R5) S29GL064A (Model R6, R7 A21– DQ15–DQ0 CE# (A-1) OE# WE# ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are ini- tiated through the internal command register. The command register itself does not occupy any addressable ...
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The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and the ...
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Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is sepa- rate from the ...
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Table 2. S29GL064A Top Boot Sector Architecture Sector Address Sector A21–A12 SA0 0000000xxx SA1 0000001xxx SA2 0000010xxx SA3 0000011xxx SA4 0000100xxx SA5 0000101xxx SA6 0000110xxx SA7 0000111xxx SA8 0001000xxx SA9 0001001xxx SA10 0001010xxx SA11 0001011xxx SA12 0001100xxx SA13 0001101xxx SA14 ...
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Table 2. S29GL064A Top Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA36 0100100xxx SA37 0100101xxx SA38 0100110xxx SA39 0100111xxx SA40 0101000xxx SA41 0101001xxx SA42 0101010xxx SA43 0101011xxx SA44 0101100xxx SA45 0101101xxx SA46 ...
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Table 2. S29GL064A Top Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA72 1001000xxx SA73 1001001xxx SA74 1001010xxx SA75 1001011xxx SA76 1001100xxx SA77 1001101xxx SA78 1001110xxx SA79 1001111xxx SA80 1010000xxx SA81 1010001xxx SA82 1010010xxx SA83 1010011xxx SA84 1010100xxx SA85 1010101xxx ...
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Table 2. S29GL064A Top Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA108 1101100xxx SA109 1101101xxx SA110 1101110xxx SA111 1101111xxx SA112 1110000xxx SA113 1110001xxx SA114 1110010xxx SA115 1110011xxx SA116 1110100xxx SA117 1110101xxx SA118 ...
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Table 3. S29GL064A Bottom Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA6 0000000110 SA7 0000000111 SA8 0000001xxx SA9 0000010xxx SA10 0000011xxx SA11 0000100xxx SA12 0000101xxx SA13 0000110xxx SA14 0000111xxx SA15 0001000xxx SA16 0001001xxx SA17 0001010xxx SA18 0001011xxx SA19 0001100xxx ...
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Table 3. S29GL064A Bottom Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA42 0101011xxx SA43 0100100xxx SA44 0100101xxx SA45 0100110xxx SA46 0100111xxx SA47 0101000xxx SA48 0101001xxx SA49 0101010xxx SA50 0101011xxx SA51 0101100xxx SA52 ...
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Table 3. S29GL064A Bottom Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA78 1000111xxx SA79 1001000xxx SA80 1001001xxx SA81 1001010xxx SA82 1001011xxx SA83 1001100xxx SA84 1001101xxx SA85 1001110xxx SA86 1001111xxx SA87 1010000xxx SA88 1010001xxx SA89 1010010xxx SA90 1010011xxx SA91 1010100xxx ...
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Table 3. S29GL064A Bottom Boot Sector Architecture (Continued) Sector Address Sector A21–A12 SA114 1101011xxx SA115 1101100xxx SA116 1101101xxx SA117 1101110xxx SA118 1101111xxx SA119 1110000xxx SA120 1110001xxx SA121 1110010xxx SA122 1110011xxx SA123 1110100xxx SA124 ...
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Table 4. Autoselect Codes, (High Voltage Method) WE Description CE# OE# # Manufacturer ID: Spansion Products Cycle 1 Cycle Cycle 3 Sector Group Protection Verification Secured Silicon Sector Indicator Bit ...
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Table 5. S29GL064A Sector Group Protection/Unprotection Address Top Boot Sector Sector Group SA0 SA1 SA2 SA3 SA4–SA7 SA8–SA11 SA12–SA15 SA16–SA19 SA20–SA23 SA24–SA27 SA28–SA31 SA32–SA35 SA36–SA39 SA40–SA43 SA44–SA47 SA48–SA51 SA52–SA55 SA56–SA59 SA60–SA63 SA64–SA67 SA68–SA71 ...
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Temporary Sector Group Unprotect This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin During this mode, formerly protected sector groups ...
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START PLSCNT = 1 RESET Wait 1 µs Temporary Sector No First Write Group Unprotect Cycle = 60h? Mode Yes Set up sector group address Sector Group Protect: Write 60h ...
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Secured Silicon Sector Flash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured ...
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Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the ...
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Power-Up Write Inhibit If WE the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines ...
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Addresses (x16) Addresses (x8) 10h 20h 11h 22h 12h 24h 13h 26h 14h 28h 15h 2Ah 16h 2Ch 17h 2Eh 18h 30h 19h 32h 1Ah 34h Addresses (x16) Addresses (x8) 1Bh 36h 1Ch ...
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Addresses (x16) Addresses (x8) 27h 4Eh 28h 50h 29h 52h 2Ah 54h 2Bh 56h 2Ch 58h 2Dh 5Ah 2Eh 5Ch 2Fh 5Eh 30h 60h 31h 60h 32h 64h 33h 66h 34h 68h 35h 6Ah 36h 6Ch 37h 6Eh 38h 70h ...
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Addresses (x16) Addresses (x8) 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h 4Dh 9Ah 4Eh 9Ch 4Fh 9Eh 50h A0h February 8, 2005 S71GL064A_00_A2 ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is ...
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Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific addresses: Identifier Code Manufacturer ID Device ID, Cycle 1 Device ID, Cycle 2 Device ID, ...
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Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the same word address multiple times without intervening erases (incremen- tal bit programming) requires a modified programming method. For such application requirements, please contact your ...
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Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a ...
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The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than ...
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Yes (Note 1) No DQ1 = 1? Yes (Note 2) (Note 3) Figure 3. Write Buffer Programming Operation February 8, 2005 S71GL064A_00_A2 ...
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Increment Address Note:See Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program ...
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The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another ...
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No Figure 5. Program Suspend/Program Resume Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writ- ing two unlock cycles, followed by a set-up command. Two additional unlock write ...
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Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles ...
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Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Op- erations table in the AC Characteristics section for parameters, and timing diagrams. Notes: 1. See Table 10 for program command sequence. 2. See the ...
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Note: During an erase operation, this flash device performs multiple internal oper- ations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not ...
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Command Definitions Table 10. Command Definitions (x16 Mode, BYTE Command Sequence (Note 1) 1 Read (Note 6) 1 Reset (Note 7) 4 Manufacturer ID 4 Device ID (Note 9) Secured Silicon Sector Factory 4 Protect (Note 10) Sector ...
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Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. of these bits. DQ7 and DQ6 each offer a ...
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Notes Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle ...
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The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. 56 ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is ac- tively erasing (that is, the Embedded Erase algorithm is in progress), or ...
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DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are ...
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Absolute Maximum Ratings Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . ...
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DC Characteristics CMOS Compatible Parameter Parameter Description Symbol (Notes) I Input Load Current (Note A9, ACC Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current Initial Read Current (Notes 2, ...
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Test Conditions Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent. Figure 11. Test Setup February 8, 2005 S71GL064A_00_A2 ...
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Key to Switching Waveforms Waveform Don’t Care, Any Change Permitted V CC Input 0 0.0 V Figure 12. Input Waveforms and Measurement Levels ...
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Characteristics Read-Only Operations-S29GL064A only Parameter JEDEC Std Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV ...
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A23-A2 A1-A0* Data Bus CE# OE# Note: Shows device in word mode. Addresses are A1–A-1 for byte mode. Hardware Reset (RESET#) Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low ...
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RY/BY# CE#, OE# RESET# t Reset Timings NOT during Embedded Algorithms RY/BY# CE#, OE# RESET# Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For ...
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Erase and Program Operations-S29GL064A Only Parameter JEDEC Std Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t Address Hold ...
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Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data ...
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Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status ...
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Addresses POLL ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after ...
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Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note:DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Temporary Sector Unprotect Parameter JEDEC ...
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RESET# SA, A6, A3, A2, A1, A0 Sector Group Protect or Unprotect Data 60h 1 µs CE# WE# OE# Note: For sector group protect, A6:A0 = 0xx0010. For sector ...
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AC Characteristics Alternate CE# Controlled Erase and Program Operations-S29GL064A Parameter JEDEC Std Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup Time ...
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PBA for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or ...
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Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time Total Write Buffer Program Time (Notes 3, 5) Total Accelerated Effective Write Buffer Program Time (Notes 4, 5) Chip Program Time Notes: 1. Typical program and erase times assume ...
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pSRAM Type 1 4Mbit (256K Word x 16-bit) 8Mbit (512K Word x 16-bit) 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) Functional Description Mode CE# CE2/ZZ# ...
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DC Characteristics Symbol Parameter V Power Supply CC V Input High Level IH V Input Low Level IL Input Leakage I IL Current Output Leakage I LO Current Output High V OH Voltage Output Low V OL Voltage Operating I ...
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Table 14. 8Mb pSRAM Asynchronous (Continued) Version Performance Grade Density Symbol Parameter Conditions Output High Voltage -0.5 mA ...
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Table 15. 16Mb pSRAM Asynchronous (Continued) Symbol Parameter I 1/2 Array PAR Current PAR 1/2 Performance Grade Density Symbol Parameter Conditions V Power Supply CC Input High V IH Level Input Low V IL Level Input Leakage I Vin = ...
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Version Performance Grade Density Symbol Parameter Conditions Power V CC Supply Input High V IH Level Input Low V IL Level Input I Leakage Vin = Current Output ...
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Table 18. 64Mb pSRAM Page Mode (Continued) Symbol Parameter Input Leakage I IL Current Output Leakage I LO Current Output High V OH Voltage Output Low V OL Voltage Operating I ACTIVE Current I Standby Current STANDBY I Deep Power ...
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Output Load Circuit Power Up Sequence After applying power, maintain a stable power supply for a minimum of 200 µs after CE# > February 8, 2005 S71GL064A_00_A2 ...
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AC Characteristics 3 Volt Table 19. 4Mb pSRAM Page Mode Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter Min Max ...
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Table 19. 4Mb pSRAM Page Mode (Continued) 3 Volt February 8, 2005 S71GL064A_00_A2 Asynchronous Performance Grade -70 Density 4Mb pSRAM Symbol Parameter ...
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Version Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output UB#, LB# Access tba time Chip select to tlz Low-z output UB#, LB# ...
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Table 20. 8Mb pSRAM Asynchronous (Continued) Version Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chip select to tcw end of write Address set up tas Time Address valid to ...
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Performance Grade 3 Volt Symbol trc taa tco toe tba tlz tblz tolz thz tbhz tohz toh twc tcw tas taw tbw twp twr twhz tdw tdh tow tow ...
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Figure 26. 16Mb pSRAM Asynchronous (Continued) Performance Grade 3 Volt Symbol tpc tpa twpc tcp Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to ...
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Table 21. 16Mb pSRAM Page Mode (Continued) Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chipselect to end tcw of write Address set up tas Time Address valid to taw end of write UB#, LB# valid tbw ...
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Version Performance Grade Density 3 Volt Symbol Parameter trc Read cycle time Address Access taa Time Chip select to tco output Output enable to toe valid output UB#, LB# Access tba time Chip ...
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Table 22. 32Mb pSRAM Page Mode (Continued) Version Performance Grade Density 3 Volt Symbol Parameter twc Write cycle time Chipselect to end tcw of write Address set up tas Time Address valid to taw end of write UB#, LB# valid ...
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Volt February 8, 2005 S71GL064A_00_A2 Table 23. 64Mb pSRAM Page Mode Page Mode Performance Grade -70 Density 64Mb pSRAM Symbol Parameter ...
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Table 23. 64Mb pSRAM Page Mode (Continued) 3 Volt Timing Diagrams Read Cycle Address Previous Data Valid Data Out Figure 27. Timing of Read Cycle (CE ...
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Address CE# OE# LB#, UB# High-Z Data Out Figure 28. Timing Waveform of Read Cycle (WE February 8, 2005 S71GL064A_00_A2 ...
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Page Address (A4 - A20) Word Address (A0 - A3) CE# OE# LB#, UB# High-Z Data Out Figure 29. Timing Waveform of Page Mode Read Cycle (WE ...
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Write Cycle Addr es s CE# LB#, UB# WE# High-Z Dat Out Figure 30. Timing Waveform of Write Cycle (WE# Control, ZZ dres s CE# LB#, ...
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Page A ddr 20) Wor d A ddr CE# WE# LB#, UB# High-Z Dat a Out Figure 32. Timing Waveform of Page Mode Write Cycle (ZZ# = ...
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tings for the PASR operation are defined in ZZ# is active low, only the portion of the array that is set in the register is re- freshed. The data in the remainder of ...
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A21 - A8 A7 Reserved Must set to all 0 Page Mode 0 = Page Mode Disabled (default Page Mode Enabled Address CE# WE# t CDZZ ZZ# Figure 34. Mode Register UpdateTimings (UB#, LB#, OE# are Don’t Care) ...
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ZZ# t CDZZ CE# Figure 35. Deep Sleep Mode - Entry/Exit Timings (for 64M CE# WE# LB#, UB# t ZZWE ZZ# Figure 36. Deep Sleep Mode - Entry/Exit Timings (for ...
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Table 25. Address Patterns for PASR (A4=1) (64M) (Continued Active Section PASR Bottom quarter of die Bottom half of die Reserved ...
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Table 28. Address Patterns for RMS ( (32M) (Continued Active Section One-quarter of die One-half of die Table 29. ...
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Type 7 16Mb (1M word x 16-bit) 32Mb (2M word x 16-bit) 64Mb (4M word x 16-bit) CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low Power SRAM Interface Features Asynchronous SRAM Interface Fast Access Time — ...
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Functional Description Mode CE2# Standby (Deselect) H Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word Write Write (Upper Byte) Write (Lower Byte) Write ...
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Power Down Program Sequence The program requires 6 read/write operations with a unique address. Between each read/write operation requires that device be in standby mode. The following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th ...
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Absolute Maximum Ratings Item Voltage of V Supply Relative Voltage at Any Pin Relative to V Short Circuit Output Current Storage temperature WARNING: Semiconductor devices can be permanently damaged by ...
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DC Characteristics (Under Recommended Conditions Unless Otherwise Noted) Parameter Symbol Input Leakage Current Output Leakage OUT Current Output High Voltage Level ...
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Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted) Read Operation Parameter Read Cycle Time CE1# Access Time OE# Access Time Address Access Time LB# / UB# Access Time Page Address Access Time ...
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AC Characteristics Write Operation Parameter Write Cycle Time Address Setup Time CE1# Write Pulse Width WE# Write Pulse Width LB#/UB# Write Pulse Width LB#/UB# Byte Mask Setup Time LB#/UB# Byte Mask Hold Time Write Recovery Time CE1# High Pulse Width ...
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Characteristics Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit ...
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AC Characteristics AC Test Conditions Symbol Description V Input High Level IH V Input Low Level IL V Input Timing Measurement Level REF t Input Transition Time T AC Measurement Output Load Circuits V DD 0.1 µ ...
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Timing Diagrams Read Timings ADDRESS t ASC CE1# OE# LB#/ UB# DQ (Output) Note: This timing diagram assumes CE2=H and WE#=H. ADDRESS ADDRESS VALID CE1# Low t ASO OE# LB#/UB# DQ (Output) Note: ...
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AX ADDRESS t AA Low CE1#, OE# t LB# UB# DQ1-8 (Output) DQ9-16 (Output) Note: This timing diagram assumes CE2=H and WE#=H. Figure 41. Read Timing #3 (LB#/UB# Byte Access) ADDRESS (A21-A3 ADDRESS ADDRESS VALID (A2-A0) t ...
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ADDRESS ADDRESS VALID (A21-A3 ADDRESS ADDRESS VALID (A2-A0 CE1# Low t t ASO OE OE LB#/UB# t OLZ t BLZ DQ (Output) Notes: 1. This timing diagram ...
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ADDRESS t OHAH CE1# Low t AS WE# LB#, UB# t OES OE# t OHZ DQ (Input) Note:This timing diagram assumes CE2=H. Figure 45. Write Timing #2 (WE# Control) ADDRESS CE1# Low t AS WE# LB UB# DQ1-8 ...
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ADDRESS CE1# Low WE LB UB# DQ1-8 (Input) DQ9-16 (Input) Note: This timing diagram assumes CE2=H and OE#=H. Figure 47. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) ADDRESS CE1# ...
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Read/Write Timings ADDRESS t t CHAH AS CE1 WE# UB#, LB# t OHCL OE# t CHZ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. Write address is valid from either CE1# or ...
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ADDRESS t OHAH CE1# Low t AS WE# t OES UB#, LB# OE# t OHZ READ DATA OUTPUT Notes: 1. This timing diagram assumes CE2=H. 2. CE1# can be tied ...
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CE1# CE2 Note: The t specifies after V C2LH DD CE1# CE2 Note: The t specifies after V reaches specified minimum level and applicable to both CE1# and CE2. CHH DD CE1# CE2 t ...
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CE1# OE# WE# Active (Read) Note: Both t and t define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes CHOX CHWX t (min) period for ...
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Type 1 SRAM 4/8 Megabit CMOS SRAM Common Features Process Technology: Full CMOS Power Supply Voltage: 2.7~3.3V Three state outputs Version Density F 4Mb G 4Mb C 8Mb D 8Mb Notes: 1. UB#, LB# swapping is available only at x16. ...
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Functional Description 4M Version F, 4M version G, 8M version C CS1# CS2 OE# WE# BYTE ...
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Functional Description 8M Version D CS1# CS2 OE# WE# LB ...
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Characteristics Recommended DC Operating Conditions (Note 1) Item Symbol Supply voltage V CC Ground V SS Input high voltage V IH Input low voltage V IL Notes: ° -40 ...
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Version F Item Symbol I CC1 Average operating current I CC2 I SB1 Standby Current (CMOS) (Note) Note: Typical values are not 100% tested. 4M Version G Item Symbol I CC1 Average operating current I CC2 I SB1 Standby ...
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Version C Item Symbol I CC1 Average operating current I CC2 I SB1 Standby Current (CMOS) (Note) Note: Typical values are not 100% tested. 8M Version D Item Symbol I CC1 Average ...
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AC Operating Conditions Test Conditions Test Load and Test Input/Output Reference Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See Figure 58): CL= 30pF+1TTL Notes: 1. Including scope ...
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Table 33. Read/Write Characteristics (V Parameter List Write cycle time Chip select to end of write Address set-up time Address valid to end of write LB#, UB# valid to end of write Write ...
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Version G Item Symbol V for data retention Data retention current I DR Data retention set-up time t SDR Recovery time t RDR Notes: ≥ 1. CS1 controlled:CS1# V -0.2V. CS2 controlled: CS2 ≤ 0.2V. CC ...
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Address CS1# CS2 UB#, LB# OE# Data out High-Z Notes and t are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to ...
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Address CS1# CS2 UB#, LB# WE# Data in Data out Figure 62. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing) Address CS1# CS2 UB#, LB# WE# Data in Data out Notes write ...
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CS1# Controlled V CC 2.7V 2. CS1# GND CS2 Controlled V CC 2.7V CS2 V DR 0.4V GND February 8, 2005 S71GL064A_00_A2 ...
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Revision Summary Revision A (October 28, 2004) Initial release. Revision A1 (December 7, 2004) Global Access speed updated. MCP Block Diagram Control signals updated. Pin Description Descriptions updated. Ordering Information Package Modifiers and pSRAM densities updated. Valid Combinations table Speed ...